soc/amd/stoneyridge: provide alternate monotonic timer

The TSC has been observed to be ticking at a non-constant rate
in early boot. The root cause is still not known, but this
misbehavior necessitates an alternative monotonic timer source.
Use the perf TSC which ticks at 100 MHz. This also means the
timestamp table is not accurate as well. Root cause of TSC rate
instability needs to be resolved in order to fix that.

BUG=b:72170796

Change-Id: Ie052169868a9d9f25f8cc0ce8dd8251b560e671f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>

3 files changed, 38 insertions, 1 deletions

diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 51573fe34f..4f07db8a39 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -39,7 +39,6 @@ config CPU_SPECIFIC_OPTIONS
 	select HAVE_HARD_RESET
 	select UDELAY_TSC
 	select HAVE_MONOTONIC_TIMER
-	select TSC_MONOTONIC_TIMER
 	select TSC_CONSTANT_RATE
 	select SPI_FLASH if HAVE_ACPI_RESUME
 	select TSC_SYNC_LFENCE
diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index 87d355bd1e..e043caf63a 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -41,6 +41,7 @@ bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c
 bootblock-y += BiosCallOuts.c
 bootblock-y += bootblock/bootblock.c
 bootblock-y += i2c.c
+bootblock-y += monotonic_timer.c
 bootblock-y += pmutil.c
 bootblock-y += reset.c
 bootblock-y += sb_util.c
@@ -53,6 +54,7 @@ romstage-y += romstage.c
 romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
 romstage-y += gpio.c
 romstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c
+romstage-y += monotonic_timer.c
 romstage-y += pmutil.c
 romstage-y += reset.c
 romstage-y += sb_util.c
@@ -64,12 +66,14 @@ romstage-y += tsc_freq.c
 romstage-y += southbridge.c
 
 verstage-y += i2c.c
+verstage-y += monotonic_timer.c
 verstage-y += sb_util.c
 verstage-y += pmutil.c
 verstage-y += reset.c
 verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
 verstage-y += tsc_freq.c
 
+postcar-y += monotonic_timer.c
 postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c
 postcar-y += ramtop.c
 
@@ -81,6 +85,7 @@ ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
 ramstage-y += gpio.c
 ramstage-y += hda.c
+ramstage-y += monotonic_timer.c
 ramstage-y += southbridge.c
 ramstage-y += sb_util.c
 ramstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c
@@ -100,6 +105,7 @@ ramstage-y += usb.c
 ramstage-y += tsc_freq.c
 ramstage-$(CONFIG_SPI_FLASH) += spi.c
 
+smm-y += monotonic_timer.c
 smm-y += smihandler.c
 smm-y += smi_util.c
 smm-y += sb_util.c
diff --git a/src/soc/amd/stoneyridge/monotonic_timer.c b/src/soc/amd/stoneyridge/monotonic_timer.c
new file mode 100644
index 0000000000..170a640233
--- /dev/null
+++ b/src/soc/amd/stoneyridge/monotonic_timer.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/msr.h>
+#include <timer.h>
+
+#define CU_PTSC_MSR	0xc0010280
+#define PTSC_FREQ_MHZ	100
+
+void timer_monotonic_get(struct mono_time *mt)
+{
+	unsigned long long val;
+	msr_t msr;
+
+	msr = rdmsr(CU_PTSC_MSR);
+
+	val = ((unsigned long long)msr.hi << 32) | msr.lo;
+
+	mono_time_set_usecs(mt, val / PTSC_FREQ_MHZ);
+}