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authorPatrick Rudolph <siro@das-labor.org>2017-04-12 16:54:55 +0200
committerMartin Roth <martinroth@google.com>2017-05-01 16:22:52 +0200
commit2be2840a1da29ed50b6eba6c2b7ba68579782a91 (patch)
treeac195abbc2bdb3559032b396c6d128ca4a1e1e0d /src
parentd0eb6cd8bd89ee47a8e3bf2948a2ff4196c761e3 (diff)
downloadcoreboot-2be2840a1da29ed50b6eba6c2b7ba68579782a91.tar.xz
nb/intel/nehalem/gma: Set up OpRegion in nb code
Set up IGD OpRegion in northbridge and fill in GNVS' aslb. At this point GNVS already has been set up by SSDT injection. Required for future VBT patches that will: * Use ACPI memory instead of CBMEM * Use common implementation to locate VBT * Fill in platform specific values Change-Id: I76b31fe5fd19b50b82f57748558fb04408e0fd23 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19309 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/northbridge/intel/nehalem/gma.c27
-rw-r--r--src/southbridge/intel/ibexpeak/lpc.c6
2 files changed, 27 insertions, 6 deletions
diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c
index 4e57b0f313..daa6ec4df1 100644
--- a/src/northbridge/intel/nehalem/gma.c
+++ b/src/northbridge/intel/nehalem/gma.c
@@ -29,6 +29,8 @@
#include <pc80/vga.h>
#include <pc80/vga_io.h>
#include <drivers/intel/gma/intel_bios.h>
+#include <southbridge/intel/ibexpeak/nvs.h>
+#include <cbmem.h>
#include "chip.h"
#include "nehalem.h"
@@ -1095,6 +1097,30 @@ static void gma_ssdt(device_t device)
drivers_intel_gma_displays_ssdt_generate(gfx);
}
+static unsigned long
+gma_write_acpi_tables(struct device *const dev,
+ unsigned long current,
+ struct acpi_rsdp *const rsdp)
+{
+ igd_opregion_t *opregion;
+ global_nvs_t *gnvs;
+
+ // FIXME: Replace by common VBT implementation writing to current
+ opregion = igd_make_opregion();
+ if (opregion) {
+ /* GNVS has been already set up */
+ gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
+ if (gnvs) {
+ /* IGD OpRegion Base Address */
+ gnvs->aslb = (u32)(uintptr_t)opregion;
+ } else {
+ printk(BIOS_ERR, "Error: GNVS table not found.\n");
+ }
+ }
+
+ return current;
+}
+
static struct pci_operations gma_pci_ops = {
.set_subsystem = gma_set_subsystem,
};
@@ -1108,6 +1134,7 @@ static struct device_operations gma_func0_ops = {
.scan_bus = 0,
.enable = 0,
.ops_pci = &gma_pci_ops,
+ .write_acpi_tables = gma_write_acpi_tables,
};
static const unsigned short pci_device_ids[] = {
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 0a08a15399..f01d8b20c0 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -620,10 +620,6 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
static void southbridge_inject_dsdt(device_t dev)
{
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
- void *opregion;
-
- /* Calling northbridge code as gnvs contains opregion address. */
- opregion = igd_make_opregion();
if (gnvs) {
const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
@@ -637,8 +633,6 @@ static void southbridge_inject_dsdt(device_t dev)
gnvs->ndid = gfx->ndid;
memcpy(gnvs->did, gfx->did, sizeof(gnvs->did));
- /* IGD OpRegion Base Address */
- gnvs->aslb = (u32)opregion;
/* And tell SMI about it */
smm_setup_structures(gnvs, NULL, NULL);