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| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-01-22 20:13:49 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-02-22 10:11:00 +0000 |
| commit | 2e81f394cffc6f1993a5f004356ed35f6064fe48 (patch) | |
| tree | 8b167143aba6e3a9a32e338e909f4e453eb4f5e9 /src | |
| parent | fc31e44e47751a7cbffea19920f1f5ef34c6bc13 (diff) | |
| download | coreboot-2e81f394cffc6f1993a5f004356ed35f6064fe48.tar.xz | |
mainboard/google/meowth: enable PCH iSCLK
Turn on PCH iSCLK for meowth platform.
BUG=None
TEST=Boot up into OS and check register programming with iotools, the
command is iotools mmio_read32 0xfdad8000, returned value is 0x03.
Change-Id: I1e44e3748c9b37c8f60adcc47a866d445d77cfaa
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23368
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/zoombini/variants/meowth/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb index 796b816274..20654e39d8 100644 --- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb @@ -53,6 +53,9 @@ chip soc/intel/cannonlake register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" + # Enable Pch iSCLK + register "pch_isclk" = "1" + # Touchscreen Digitizer register "i2c[0]" = "{ .speed = I2C_SPEED_FAST_PLUS, |