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authorGaggery Tsai <gaggery.tsai@intel.com>2017-11-02 09:58:06 +0800
committerMartin Roth <martinroth@google.com>2017-11-09 18:39:12 +0000
commit2ecf3f8cb9784ce14752878a5a63c9359a7726a7 (patch)
treeb7f87fd0ff7a5c093055cd46019a4ac2da311d99 /src
parente0a6ee888096a74791196c3b2a627afebb0ccd2c (diff)
downloadcoreboot-2ecf3f8cb9784ce14752878a5a63c9359a7726a7.tar.xz
mb/google/fizz: Enable NIC leds
This patch enables customized NIC leds as follows: Green Orange (Amber) 100M off blinking 1000M on blinking BUG=b:65437780, b:68284778 TEST=Make sure the registers are programmed as expected and observe the LEDs are behaving as expected. Perform suspend/resume test and the LEDs are still working as expected. Change-Id: I9bb1367a4c742c2755d620e14ee6dfe70ee7f34b Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/22293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/fizz/Kconfig1
-rw-r--r--src/mainboard/google/fizz/devicetree.cb10
2 files changed, 9 insertions, 2 deletions
diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig
index 1431db42c6..64748243fa 100644
--- a/src/mainboard/google/fizz/Kconfig
+++ b/src/mainboard/google/fizz/Kconfig
@@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS
select FIZZ_USE_SPI_TPM
select GENERIC_SPD_BIN
select RT8168_GET_MAC_FROM_VPD
+ select RT8168_SET_LED_MODE
select SPD_READ_BY_WORD
config VBOOT
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb
index 15902528af..73a5c5077d 100644
--- a/src/mainboard/google/fizz/devicetree.cb
+++ b/src/mainboard/google/fizz/devicetree.cb
@@ -302,9 +302,15 @@ chip soc/intel/skylake
end
end # I2C #5
device pci 19.2 off end # I2C #4
- device pci 1c.0 on end # PCI Express Port 1
+ device pci 1c.0 on # PCI Express Port 1
+ chip drivers/net
+ register "customized_leds" = "0x0fa7"
+ device pci 00.0 on end
+ end
+ end # PCI Express Port 1
device pci 1c.1 off end # PCI Express Port 2
- device pci 1c.2 on end # PCI Express Port 3 for LAN
+ # PCI Express Port 3 for LAN, but will be swapped to port 1
+ device pci 1c.2 on end
device pci 1c.3 on
chip drivers/intel/wifi
register "wake" = "GPE0_PCI_EXP"