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authorVladimir Serbinenko <phcoder@gmail.com>2014-02-05 23:25:28 +0100
committerVladimir Serbinenko <phcoder@gmail.com>2014-02-06 00:55:13 +0100
commit30fe6120ca8d7211f0055e47d3ecd569a628f2aa (patch)
tree52906b5ed573d84a207e78bf9425988602cf1b97 /src
parent7a4fa0a32cf11a0686804afffbcd02827c846fcf (diff)
downloadcoreboot-30fe6120ca8d7211f0055e47d3ecd569a628f2aa.tar.xz
MTRR: Mark all prefetchable resources as WRCOMB.
Change-Id: I2ecfd9733b65b6160bc2232d22db7b16692a847f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5149 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/arch/x86/Kconfig8
-rw-r--r--src/cpu/x86/mtrr/mtrr.c5
-rw-r--r--src/include/device/resource.h1
-rw-r--r--src/mainboard/google/bolt/Kconfig1
-rw-r--r--src/mainboard/google/falco/Kconfig1
-rw-r--r--src/mainboard/google/link/Kconfig1
-rw-r--r--src/mainboard/google/peppy/Kconfig1
-rw-r--r--src/mainboard/google/rambi/Kconfig1
-rw-r--r--src/mainboard/google/slippy/Kconfig1
-rw-r--r--src/mainboard/intel/wtm2/Kconfig1
-rw-r--r--src/northbridge/intel/haswell/gma.c19
-rw-r--r--src/northbridge/intel/nehalem/gma.c3
-rw-r--r--src/northbridge/intel/sandybridge/gma.c19
13 files changed, 4 insertions, 58 deletions
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 0a21fcc99a..8854e6b07b 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -7,14 +7,6 @@ config X86_ARCH_OPTIONS
select HAVE_ARCH_MEMCPY
select HAVE_ARCH_MEMMOVE
-config MARK_GRAPHICS_MEM_WRCOMB
- bool "Mark graphics memory as write-combining."
- default n
- help
- The graphics performance may increase if the graphics
- memory is set as write-combining cache type. This option
- enables marking the graphics memory as write-combining.
-
# This is an SMP option. It relates to starting up APs.
# It is usually set in mainboard/*/Kconfig.
# TODO: Improve description.
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index cdaa791de3..dfb9c94eeb 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -178,9 +178,8 @@ static struct memranges *get_physical_address_space(void)
MTRR_TYPE_UNCACHEABLE);
/* Handle any write combining resources. Only prefetchable
- * resources with the IORESOURCE_WRCOMB flag are appropriate
- * for this MTRR type. */
- match = IORESOURCE_PREFETCH | IORESOURCE_WRCOMB;
+ * resources are appropriate for this MTRR type. */
+ match = IORESOURCE_PREFETCH;
mask |= match;
memranges_add_resources(addr_space, mask, match,
MTRR_TYPE_WRCOMB);
diff --git a/src/include/device/resource.h b/src/include/device/resource.h
index 4bd9698e2c..2d64c805af 100644
--- a/src/include/device/resource.h
+++ b/src/include/device/resource.h
@@ -21,7 +21,6 @@
* to the bus below.
*/
#define IORESOURCE_BRIDGE 0x00080000 /* The IO resource has a bus below it. */
-#define IORESOURCE_WRCOMB 0x00100000 /* Write combining resource. */
#define IORESOURCE_RESERVE 0x10000000 /* The resource needs to be reserved in the coreboot table */
#define IORESOURCE_STORED 0x20000000 /* The IO resource assignment has been stored in the device */
#define IORESOURCE_ASSIGNED 0x40000000 /* An IO resource that has been assigned a value */
diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig
index 1d2b2594d2..5247070e58 100644
--- a/src/mainboard/google/bolt/Kconfig
+++ b/src/mainboard/google/bolt/Kconfig
@@ -19,7 +19,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_HAS_CHROMEOS
select EXTERNAL_MRC_BLOB
select CACHE_ROM
- select MARK_GRAPHICS_MEM_WRCOMB
select MONOTONIC_TIMER_MSR
config VBOOT_RAMSTAGE_INDEX
diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig
index b372c4714e..d8002060f1 100644
--- a/src/mainboard/google/falco/Kconfig
+++ b/src/mainboard/google/falco/Kconfig
@@ -19,7 +19,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_HAS_CHROMEOS
select EXTERNAL_MRC_BLOB
select CACHE_ROM
- select MARK_GRAPHICS_MEM_WRCOMB
select MONOTONIC_TIMER_MSR
select DRIVERS_I2C_RTD2132
diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig
index d1e809eed7..efe9519bb2 100644
--- a/src/mainboard/google/link/Kconfig
+++ b/src/mainboard/google/link/Kconfig
@@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SERIRQ_CONTINUOUS_MODE
select MAINBOARD_HAS_NATIVE_VGA_INIT
select EARLY_CBMEM_INIT
- select MARK_GRAPHICS_MEM_WRCOMB
config MAINBOARD_DIR
string
diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig
index 7a406e11f3..6cac4766ab 100644
--- a/src/mainboard/google/peppy/Kconfig
+++ b/src/mainboard/google/peppy/Kconfig
@@ -19,7 +19,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_HAS_CHROMEOS
select EXTERNAL_MRC_BLOB
select CACHE_ROM
- select MARK_GRAPHICS_MEM_WRCOMB
select MONOTONIC_TIMER_MSR
config VBOOT_RAMSTAGE_INDEX
diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig
index 4d149c9b5f..292d321388 100644
--- a/src/mainboard/google/rambi/Kconfig
+++ b/src/mainboard/google/rambi/Kconfig
@@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_ACPI_RESUME
select MAINBOARD_HAS_CHROMEOS
select CHROMEOS
- select MARK_GRAPHICS_MEM_WRCOMB
config MAINBOARD_DIR
string
diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig
index 065830ad66..6980234caa 100644
--- a/src/mainboard/google/slippy/Kconfig
+++ b/src/mainboard/google/slippy/Kconfig
@@ -19,7 +19,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_HAS_CHROMEOS
select EXTERNAL_MRC_BLOB
select CACHE_ROM
- select MARK_GRAPHICS_MEM_WRCOMB
select MONOTONIC_TIMER_MSR
select MAINBOARD_HAS_NATIVE_VGA_INIT
select MAINBOARD_DO_NATIVE_VGA_INIT
diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig
index 99ed53cf38..8e13108af3 100644
--- a/src/mainboard/intel/wtm2/Kconfig
+++ b/src/mainboard/intel/wtm2/Kconfig
@@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_SMI_HANDLER
select MAINBOARD_HAS_CHROMEOS
select CACHE_ROM
- select MARK_GRAPHICS_MEM_WRCOMB
select MAINBOARD_HAS_NATIVE_VGA_INIT
select MONOTONIC_TIMER_MSR
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 00d7583048..2ceffe4a83 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -429,29 +429,12 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
}
}
-static void gma_read_resources(struct device *dev)
-{
- pci_dev_read_resources(dev);
-
-#if CONFIG_MARK_GRAPHICS_MEM_WRCOMB
- struct resource *res;
-
- /* Set the graphics memory to write combining. */
- res = find_resource(dev, PCI_BASE_ADDRESS_2);
- if (res == NULL) {
- printk(BIOS_DEBUG, "gma: memory resource not found.\n");
- return;
- }
- res->flags |= IORESOURCE_WRCOMB;
-#endif
-}
-
static struct pci_operations gma_pci_ops = {
.set_subsystem = gma_set_subsystem,
};
static struct device_operations gma_func0_ops = {
- .read_resources = gma_read_resources,
+ .read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = gma_func0_init,
diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c
index c7a0e9b941..2f13a6bee6 100644
--- a/src/northbridge/intel/nehalem/gma.c
+++ b/src/northbridge/intel/nehalem/gma.c
@@ -703,9 +703,6 @@ static void gma_read_resources(struct device *dev)
0xd0000001);
pci_write_config32(dev, PCI_BASE_ADDRESS_2 + 4,
0);
-#if CONFIG_MARK_GRAPHICS_MEM_WRCOMB
- res->flags |= IORESOURCE_WRCOMB;
-#endif
res->base = (resource_t) 0xd0000000;
res->size = (resource_t) 0x10000000;
}
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index 853139eddf..b9a07a2d72 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -664,29 +664,12 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
}
}
-static void gma_read_resources(struct device *dev)
-{
- pci_dev_read_resources(dev);
-
-#if CONFIG_MARK_GRAPHICS_MEM_WRCOMB
- struct resource *res;
-
- /* Set the graphics memory to write combining. */
- res = find_resource(dev, PCI_BASE_ADDRESS_2);
- if (res == NULL) {
- printk(BIOS_DEBUG, "gma: memory resource not found.\n");
- return;
- }
- res->flags |= IORESOURCE_WRCOMB;
-#endif
-}
-
static struct pci_operations gma_pci_ops = {
.set_subsystem = gma_set_subsystem,
};
static struct device_operations gma_func0_ops = {
- .read_resources = gma_read_resources,
+ .read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = gma_func0_init,