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authordavid <david_wu@quantatw.com>2016-01-04 14:16:47 +0800
committerPatrick Georgi <pgeorgi@google.com>2016-01-19 16:24:51 +0100
commit3e5c12691f217477cbf30bdbfb651d2d7da9142f (patch)
tree7791f102bc948c1749cd0d03443ac41377508fab /src
parent0691f25e53e2567e3afd455e7e3dc38fc10147f3 (diff)
downloadcoreboot-3e5c12691f217477cbf30bdbfb651d2d7da9142f.tar.xz
google/lars: Enable eMMC HS400 mode
Kingston eMMC can now run under HS400 mode. BUG=chrome-os-partner:48017 BRANCH=none TEST=run consecutive boot 100 times on Lars proto Kingston SKU, and MMC errors didn't happen. Change-Id: I3c16db6111273fbbabbfba1c315edc780fe23525 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ac474bd7bd33f11904a27691e9eb61bdaf212c6b Original-Change-Id: I9e47b6ba64ac94acff7673fca86fa62bfb30edd9 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/320194 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/13004 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/lars/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb
index 689babb5a5..e858eeac74 100644
--- a/src/mainboard/google/lars/devicetree.cb
+++ b/src/mainboard/google/lars/devicetree.cb
@@ -24,7 +24,7 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "3"
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1"
- register "ScsEmmcHs400Enabled" = "0"
+ register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "0"
register "InternalGfx" = "1"
register "SkipExtGfxScan" = "1"