diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-04-22 10:44:08 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-04-22 10:44:08 +0000 |
| commit | 4292685f5adbe45bb5b23f32c3b6aaed04187f48 (patch) | |
| tree | eac43204893114327533bd41278300ac60cb3f21 /src | |
| parent | ba09695b58f7254d646618d1207840e33ca3d1d8 (diff) | |
| download | coreboot-4292685f5adbe45bb5b23f32c3b6aaed04187f48.tar.xz | |
None of the cs5536 settings in devicetree.cb were ever used and nobody noticed.
Fix it!
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5476 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
| -rw-r--r-- | src/include/cpu/amd/gx2def.h | 7 | ||||
| -rw-r--r-- | src/southbridge/amd/cs5536/cs5536.c | 24 |
2 files changed, 29 insertions, 2 deletions
diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h index a24704aa5e..ec99b95395 100644 --- a/src/include/cpu/amd/gx2def.h +++ b/src/include/cpu/amd/gx2def.h @@ -693,4 +693,11 @@ #define PMLogic_BASE ( 0x9D00) +#if !defined(__ROMCC__) && !defined(ASSEMBLY) +#if defined(__PRE_RAM__) +#else +void cpubug(void); +#endif +#endif + #endif /* CPU_AMD_GX2DEF_H */ diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c index f5de337bbe..43f3b1290e 100644 --- a/src/southbridge/amd/cs5536/cs5536.c +++ b/src/southbridge/amd/cs5536/cs5536.c @@ -527,10 +527,24 @@ void chipsetinit(void) device_t dev; msr_t msr; u32 msrnum; - struct southbridge_amd_cs5536_config *sb = - (struct southbridge_amd_cs5536_config *)dev->chip_info; + struct southbridge_amd_cs5536_config *sb; struct msrinit *csi; + dev = dev_find_device(PCI_VENDOR_ID_AMD, + PCI_DEVICE_ID_AMD_CS5536_ISA, 0); + + if (!dev) { + printk(BIOS_ERR, "CS5536 not found.\n"); + return; + } + + sb = (struct southbridge_amd_cs5536_config *)dev->chip_info; + + if (!sb) { + printk(BIOS_ERR, "CS5536 configuration not found.\n"); + return; + } + post_code(P80_CHIPSET_INIT); /* we hope NEVER to be in coreboot when S3 resumes @@ -599,6 +613,12 @@ static void southbridge_init(struct device *dev) */ printk(BIOS_ERR, "cs5536: %s\n", __func__); + + if (!sb) { + printk(BIOS_ERR, "CS5536 configuration not found.\n"); + return; + } + setup_i8259(); lpc_init(sb); uarts_init(sb); |