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authorKyösti Mälkki <kyosti.malkki@gmail.com>2017-03-15 08:07:22 +0200
committerMartin Roth <martinroth@google.com>2017-03-19 21:38:53 +0100
commit4796c32ad60933bd8c23729684414121097b0445 (patch)
treed4a717d13010eed377aa37be1ee4e7da399922e5 /src
parent85e81dfa6dffde15670a8bd142ccac5ca27aa36d (diff)
downloadcoreboot-4796c32ad60933bd8c23729684414121097b0445.tar.xz
ramstage: Align stack to 16 bytes
Some SSE instructions could take 128bit memory operands from stack. AGESA vendorcode was always built with SSE enabled, but until now stack alignment was not known to cause major issues. Seems like GCC-6.3 more likely emits instructions that depend on the 16 byte alignment of stack. Change-Id: Iea3de54f20ff242105bce5a5edbbd76b04c0116c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18823 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/arch/x86/c_start.S2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S
index 29d3a538b4..9ad2698483 100644
--- a/src/arch/x86/c_start.S
+++ b/src/arch/x86/c_start.S
@@ -110,6 +110,8 @@ _start:
*/
post_code(POST_PRE_HARDWAREMAIN) /* post fe */
+ andl $0xFFFFFFF0, %esp
+
#if CONFIG_GDB_WAIT
call gdb_hw_init
call gdb_stub_breakpoint