chromeec: Remove checks for EC in RO

This patch removes checks that ensure EC to be in RO for recovery
boot. We do not need these checks because when recovery is requested
automatically (as opposed to manually), we show 'broken' screen where
users can only reboot the device or request recovery manually.

If recovery is requested, Depthcharge will check whether EC is in RO
or not and recovery switch was pressed or not. If it's a legitimate
manual recovery, EC should be in RO. Thus, we can trust the recovery
button state it reports.

This patch removes all calls to google_chromeec_check_ec_image,
which is called to avoid duplicate memory training when recovery
is requested but EC is in RW.

BUG=b:66516882
BRANCH=none
CQ-DEPEND=CL:693008
TEST=Boot Fizz.

Change-Id: I45a874b73c46ea88cb831485757d194faa9f4c99
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/21711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

10 files changed, 0 insertions, 140 deletions

diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index c6162dcc84..136f098e71 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -182,11 +182,6 @@ void romstage_common(const struct romstage_params *params)
 
 	wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config);
 
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
-	/* Ensure the EC is in the right mode for recovery */
-	google_chromeec_early_init();
-#endif
-
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(params->bist);
 
diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
index dc1b6a66b0..892a653769 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
@@ -69,7 +69,6 @@ struct romstage_params {
  *  30.  FSP binary/FspNotify
  */
 
-void mainboard_check_ec_image(struct romstage_params *params);
 void mainboard_memory_init_params(struct romstage_params *params,
 	MEMORY_INIT_UPD *memory_params);
 void mainboard_romstage_entry(struct romstage_params *params);
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index 4bc95c94f0..d79bc2f8c0 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -146,7 +146,6 @@ void romstage_common(struct romstage_params *params)
 			hard_reset();
 		} else {
 			printk(BIOS_DEBUG, "No MRC cache found.\n");
-			mainboard_check_ec_image(params);
 		}
 	}
 
@@ -200,20 +199,6 @@ __attribute__((weak)) struct chipset_power_state *fill_power_state(void)
 	return NULL;
 }
 
-__attribute__((weak)) void mainboard_check_ec_image(
-	struct romstage_params *params)
-{
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
-	struct pei_data *pei_data;
-
-	pei_data = params->pei_data;
-	if (params->pei_data->boot_mode == ACPI_S0) {
-		/* Ensure EC is running RO firmware. */
-		google_chromeec_check_ec_image(EC_IMAGE_RO);
-	}
-#endif
-}
-
 /* Board initialization before and after RAM is enabled */
 __attribute__((weak)) void mainboard_romstage_entry(
 	struct romstage_params *params)
diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index 03d4c3bc6d..ab879c57a2 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -325,70 +325,6 @@ int google_chromeec_reboot(int dev_idx, enum ec_reboot_cmd type, uint8_t flags)
 }
 
 #ifndef __SMM__
-#ifdef __PRE_RAM__
-void google_chromeec_check_ec_image(int expected_type)
-{
-	struct chromeec_command cec_cmd;
-	struct ec_response_get_version cec_resp = { { 0 } };
-
-	cec_cmd.cmd_code = EC_CMD_GET_VERSION;
-	cec_cmd.cmd_version = 0;
-	cec_cmd.cmd_data_out = &cec_resp;
-	cec_cmd.cmd_size_in = 0;
-	cec_cmd.cmd_size_out = sizeof(cec_resp);
-	cec_cmd.cmd_dev_index = 0;
-	google_chromeec_command(&cec_cmd);
-
-	if (cec_cmd.cmd_code || cec_resp.current_image != expected_type) {
-		/* Reboot the EC and make it come back in RO mode */
-		printk(BIOS_DEBUG, "Rebooting with EC in RO mode:\n");
-		post_code(0); /* clear current post code */
-		/* Let the platform prepare for the EC taking out the system power. */
-		if (IS_ENABLED(CONFIG_VBOOT))
-			vboot_platform_prepare_reboot();
-		google_chromeec_reboot(0, EC_REBOOT_COLD, 0);
-		udelay(1000);
-		hard_reset();
-		halt();
-	}
-}
-
-/* Check for recovery mode and ensure PD/EC is in RO */
-void google_chromeec_early_init(void)
-{
-	if (!IS_ENABLED(CONFIG_CHROMEOS) || !vboot_recovery_mode_enabled())
-		return;
-
-	/* Check USB PD chip state first */
-	if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_PD))
-		google_chromeec_check_pd_image(EC_IMAGE_RO);
-
-	/* If in recovery ensure EC is running RO firmware. */
-	google_chromeec_check_ec_image(EC_IMAGE_RO);
-}
-
-void google_chromeec_check_pd_image(int expected_type)
-{
-	struct chromeec_command cec_cmd;
-	struct ec_response_get_version cec_resp = { { 0 } };
-
-	cec_cmd.cmd_code = EC_CMD_GET_VERSION;
-	cec_cmd.cmd_version = 0;
-	cec_cmd.cmd_data_out = &cec_resp;
-	cec_cmd.cmd_size_in = 0;
-	cec_cmd.cmd_size_out = sizeof(cec_resp);
-	cec_cmd.cmd_dev_index = 1; /* PD */
-	google_chromeec_command(&cec_cmd);
-
-	if (cec_cmd.cmd_code || cec_resp.current_image != expected_type) {
-		/* Reboot the PD and make it come back in RO mode */
-		printk(BIOS_DEBUG, "Rebooting PD to RO mode\n");
-		google_chromeec_reboot(1 /* PD */, EC_REBOOT_COLD, 0);
-		udelay(1000);
-	}
-}
-#endif
-
 u16 google_chromeec_get_board_version(void)
 {
 	struct chromeec_command cmd;
@@ -696,19 +632,6 @@ void google_chromeec_init(void)
 		       cec_resp.current_image);
 		ec_image_type = cec_resp.current_image;
 	}
-
-	if (cec_cmd.cmd_code ||
-	    (vboot_recovery_mode_enabled() &&
-	     (cec_resp.current_image != EC_IMAGE_RO))) {
-		/* Reboot the EC and make it come back in RO mode */
-		printk(BIOS_DEBUG, "Rebooting with EC in RO mode:\n");
-		post_code(0); /* clear current post code */
-		google_chromeec_reboot(0, EC_REBOOT_COLD, 0);
-		udelay(1000);
-		hard_reset();
-		halt();
-	}
-
 }
 
 int google_ec_running_ro(void)
diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
index 3a7cadd506..81bc9336e5 100644
--- a/src/ec/google/chromeec/ec.h
+++ b/src/ec/google/chromeec/ec.h
@@ -40,12 +40,6 @@ int google_chromeec_set_device_enabled_events(uint32_t mask);
 uint32_t google_chromeec_get_device_current_events(void);
 void google_chromeec_log_device_events(uint32_t mask);
 
-/* If recovery mode is enabled and EC is not running RO firmware reboot. */
-void google_chromeec_early_init(void);
-/* Reboot if EC firmware is not expected type. */
-void google_chromeec_check_ec_image(int expected_type);
-void google_chromeec_check_pd_image(int expected_type);
-
 int google_chromeec_check_feature(int feature);
 uint8_t google_chromeec_calc_checksum(const uint8_t *data, int size);
 u16 google_chromeec_get_board_version(void);
diff --git a/src/mainboard/google/auron/romstage.c b/src/mainboard/google/auron/romstage.c
index 22a070e011..aedc33d3ed 100644
--- a/src/mainboard/google/auron/romstage.c
+++ b/src/mainboard/google/auron/romstage.c
@@ -31,9 +31,6 @@ void mainboard_romstage_entry(struct romstage_params *rp)
 
 	post_code(0x32);
 
-	/* Ensure the EC is in the right mode for recovery */
-	google_chromeec_early_init();
-
 	/* Initialize GPIOs */
 	init_gpios(mainboard_gpio_config);
 
diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c
index f9a5fd1626..44e0923b9b 100644
--- a/src/soc/intel/baytrail/romstage/raminit.c
+++ b/src/soc/intel/baytrail/romstage/raminit.c
@@ -137,12 +137,6 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
 		reset_system();
 	} else {
 		printk(BIOS_DEBUG, "No MRC cache found.\n");
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
-		if (prev_sleep_state == ACPI_S0) {
-			/* Ensure EC is running RO firmware. */
-			google_chromeec_check_ec_image(EC_IMAGE_RO);
-		}
-#endif
 	}
 
 	/* Determine if mrc.bin is in the cbfs. */
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index c163257ec0..9990d84257 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -128,11 +128,6 @@ void * asmlinkage romstage_main(unsigned long bist,
 
 	gfx_init();
 
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
-	/* Ensure the EC is in the right mode for recovery */
-	google_chromeec_early_init();
-#endif
-
 	/* Call into mainboard. */
 	mainboard_romstage_entry(&rp);
 
diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c
index 34ab39cad7..0470beec7e 100644
--- a/src/soc/intel/broadwell/romstage/raminit.c
+++ b/src/soc/intel/broadwell/romstage/raminit.c
@@ -65,12 +65,6 @@ void raminit(struct pei_data *pei_data)
 		reset_system();
 	} else {
 		printk(BIOS_DEBUG, "No MRC cache found.\n");
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
-		if (pei_data->boot_mode == ACPI_S0) {
-			/* Ensure EC is running RO firmware. */
-			google_chromeec_check_ec_image(EC_IMAGE_RO);
-		}
-#endif
 	}
 
 	/*
diff --git a/src/vboot/vboot_loader.c b/src/vboot/vboot_loader.c
index 9aab789854..6a7e284867 100644
--- a/src/vboot/vboot_loader.c
+++ b/src/vboot/vboot_loader.c
@@ -91,22 +91,6 @@ static void vboot_prepare(void)
 		verstage_main();
 		car_set_var(vboot_executed, 1);
 		vb2_save_recovery_reason_vbnv();
-
-		/*
-		 * Avoid double memory retrain when the EC is running RW code
-		 * and a recovery request came in through an EC host event. The
-		 * double retrain happens because the EC won't be rebooted
-		 * until kernel verification notices the EC isn't running RO
-		 * code which is after memory training. Therefore, reboot the
-		 * EC after we've saved the potential recovery request so it's
-		 * not lost. Lastly, only perform this sequence on x86
-		 * platforms since those are the ones that currently do a
-		 * costly memory training in recovery mode.
-		 */
-		if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) &&
-			IS_ENABLED(CONFIG_ARCH_X86))
-			google_chromeec_early_init();
-
 	} else if (verstage_should_load()) {
 		struct cbfsf file;
 		struct prog verstage =