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authorNico Huber <nico.h@gmx.de>2018-10-06 17:56:17 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-10-22 08:34:27 +0000
commit496fb23c5df50b266aa7f20984769357ea662a20 (patch)
tree5327a40d8615f89e2508d99209c0106a7875f287 /src
parente8791361b5825d2133c778c63a520d45540dcaf2 (diff)
downloadcoreboot-496fb23c5df50b266aa7f20984769357ea662a20.tar.xz
soc/rockchip/rk3399: Convert to `board_reset()`
Change-Id: Id07e1c7fbd35393ffafda53fc7a15ec0e157d075 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/gru/Kconfig1
-rw-r--r--src/mainboard/google/gru/reset.c2
-rw-r--r--src/soc/rockchip/rk3399/sdram.c10
3 files changed, 6 insertions, 7 deletions
diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig
index 11bf18cf12..fee2dd07b3 100644
--- a/src/mainboard/google/gru/Kconfig
+++ b/src/mainboard/google/gru/Kconfig
@@ -47,7 +47,6 @@ config BOARD_SPECIFIC_OPTIONS
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_RTC
select EC_GOOGLE_CHROMEEC_SPI
- select HAVE_HARD_RESET
select MAINBOARD_FORCE_NATIVE_VGA_INIT
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_NATIVE_VGA_INIT
diff --git a/src/mainboard/google/gru/reset.c b/src/mainboard/google/gru/reset.c
index 0311d587c6..5bf7260523 100644
--- a/src/mainboard/google/gru/reset.c
+++ b/src/mainboard/google/gru/reset.c
@@ -18,7 +18,7 @@
#include "board.h"
-void do_hard_reset(void)
+void do_board_reset(void)
{
gpio_output(GPIO_RESET, 1);
}
diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c
index 97346796fe..2b084136a3 100644
--- a/src/soc/rockchip/rk3399/sdram.c
+++ b/src/soc/rockchip/rk3399/sdram.c
@@ -990,7 +990,7 @@ static void switch_to_phy_index1(const struct rk3399_sdram_params *sdram_params)
if (stopwatch_expired(&sw)) {
printk(BIOS_ERR,
"index1 frequency change overtime, reset\n");
- hard_reset();
+ board_reset();
}
}
@@ -1000,7 +1000,7 @@ static void switch_to_phy_index1(const struct rk3399_sdram_params *sdram_params)
if (stopwatch_expired(&sw)) {
printk(BIOS_ERR,
"index1 frequency done overtime, reset\n");
- hard_reset();
+ board_reset();
}
}
@@ -1009,7 +1009,7 @@ static void switch_to_phy_index1(const struct rk3399_sdram_params *sdram_params)
clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);
if (data_training(channel, sdram_params, PI_FULL_TRAINING)) {
printk(BIOS_ERR, "index1 training failed, reset\n");
- hard_reset();
+ board_reset();
}
}
}
@@ -1042,7 +1042,7 @@ void sdram_init(const struct rk3399_sdram_params *sdram_params)
*/
if (pctl_cfg(channel, sdram_params) != 0) {
printk(BIOS_ERR, "pctl_cfg fail, reset\n");
- hard_reset();
+ board_reset();
}
/* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
@@ -1052,7 +1052,7 @@ void sdram_init(const struct rk3399_sdram_params *sdram_params)
if (data_training(channel, sdram_params, PI_FULL_TRAINING)) {
printk(BIOS_ERR,
"SDRAM initialization failed, reset\n");
- hard_reset();
+ board_reset();
}
set_ddrconfig(sdram_params, channel,