diff options
| author | Jacob Garber <jgarber1@ualberta.ca> | 2019-12-27 14:18:32 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-31 15:22:43 +0000 |
| commit | 4a216475f5382d4b0ccf5fb65cd79b7ca3b32ed4 (patch) | |
| tree | 967e60522f0b58aa8cbbb382c596d3f0b3bd4f7d /src | |
| parent | d225834220cfbe59850a97092674c4d55faff757 (diff) | |
| download | coreboot-4a216475f5382d4b0ccf5fb65cd79b7ca3b32ed4.tar.xz | |
src: Remove some romcc workarounds
Now that romcc is gone, move cmos_post_init() into post.c, and remove
some preprocessor workarounds.
Change-Id: I0ee4551e476cdd1102e86e7efc74d5909f64a37b
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'src')
| -rw-r--r-- | src/console/post.c | 24 | ||||
| -rw-r--r-- | src/include/pc80/mc146818rtc.h | 27 | ||||
| -rw-r--r-- | src/northbridge/intel/gm45/bootblock.c | 4 | ||||
| -rw-r--r-- | src/superio/nsc/pc87417/pc87417.h | 4 |
4 files changed, 27 insertions, 32 deletions
diff --git a/src/console/post.c b/src/console/post.c index 8c28ceb672..a426fccac2 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -82,6 +82,30 @@ void cmos_post_log(void) } } +void cmos_post_init(void) +{ + u8 magic = CMOS_POST_BANK_0_MAGIC; + + /* Switch to the other bank */ + switch (cmos_read(CMOS_POST_BANK_OFFSET)) { + case CMOS_POST_BANK_1_MAGIC: + break; + case CMOS_POST_BANK_0_MAGIC: + magic = CMOS_POST_BANK_1_MAGIC; + break; + default: + /* Initialize to zero */ + cmos_write(0, CMOS_POST_BANK_0_OFFSET); + cmos_write(0, CMOS_POST_BANK_1_OFFSET); +#if CONFIG(CMOS_POST_EXTRA) + cmos_write32(CMOS_POST_BANK_0_EXTRA, 0); + cmos_write32(CMOS_POST_BANK_1_EXTRA, 0); +#endif + } + + cmos_write(magic, CMOS_POST_BANK_OFFSET); +} + #if CONFIG(CMOS_POST_EXTRA) void post_log_extra(u32 value) { diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index afa4d9714c..ecfa76dfbb 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -223,32 +223,7 @@ int do_normal_boot(void); #define CMOS_POST_EXTRA_DEV_PATH 0x01 void cmos_post_log(void); - -/* cmos_post_init() is exposed in this manner because it also needs to be called - * by bootblock code compiled by romcc. */ -static inline void cmos_post_init(void) -{ - u8 magic = CMOS_POST_BANK_0_MAGIC; - - /* Switch to the other bank */ - switch (cmos_read(CMOS_POST_BANK_OFFSET)) { - case CMOS_POST_BANK_1_MAGIC: - break; - case CMOS_POST_BANK_0_MAGIC: - magic = CMOS_POST_BANK_1_MAGIC; - break; - default: - /* Initialize to zero */ - cmos_write(0, CMOS_POST_BANK_0_OFFSET); - cmos_write(0, CMOS_POST_BANK_1_OFFSET); -#if CONFIG(CMOS_POST_EXTRA) - cmos_write32(CMOS_POST_BANK_0_EXTRA, 0); - cmos_write32(CMOS_POST_BANK_1_EXTRA, 0); -#endif - } - - cmos_write(magic, CMOS_POST_BANK_OFFSET); -} +void cmos_post_init(void); #else static inline void cmos_post_log(void) {} static inline void cmos_post_init(void) {} diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c index dda2b585f1..58b99ac40b 100644 --- a/src/northbridge/intel/gm45/bootblock.c +++ b/src/northbridge/intel/gm45/bootblock.c @@ -14,9 +14,7 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> -/* Just re-define these instead of including gm45.h. It blows up romcc. */ -#define D0F0_PCIEXBAR_LO 0x60 -#define D0F0_PCIEXBAR_HI 0x64 +#include "gm45.h" void bootblock_early_northbridge_init(void) { diff --git a/src/superio/nsc/pc87417/pc87417.h b/src/superio/nsc/pc87417/pc87417.h index c3fc5ef699..cb6515d8af 100644 --- a/src/superio/nsc/pc87417/pc87417.h +++ b/src/superio/nsc/pc87417/pc87417.h @@ -31,9 +31,7 @@ #define PC87417_RTC 0x10 #define PC87417_GPIO_DEV PNP_DEV(0x2e, PC87417_GPIO) -/* This is to get around a romcc bug */ -/* #define PC87417_XBUS_DEV PNP_DEV(0x2e, PC87417_XBUS) */ -#define PC87417_XBUS_DEV PNP_DEV(0x2e, 0x0f) +#define PC87417_XBUS_DEV PNP_DEV(0x2e, PC87417_XBUS) #define PC87417_GPSEL 0xf0 #define PC87417_GPCFG1 0xf1 |