Drop some duplicates of PCI-e config functions

These are not specific to Intel. Further work needs to be done to
combine these with MMCONF_SUPPORT in arch/io.h.

Change-Id: Id429db2df8d47433117c21133d80fc985b3e11e4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3502
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

16 files changed, 17 insertions, 158 deletions

diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h
index 29c83395a8..49499b97d1 100644
--- a/src/arch/x86/include/arch/io.h
+++ b/src/arch/x86/include/arch/io.h
@@ -395,6 +395,8 @@ static inline __attribute__((always_inline)) void pci_write_config32(device_t de
 #endif
 }
 
+#include <arch/pci_mmio_cfg.h>
+
 static inline __attribute__((always_inline)) void pci_or_config8(device_t dev, unsigned where, uint8_t value)
 {
 	pci_write_config8(dev, where, pci_read_config8(dev, where) | value);
diff --git a/src/northbridge/intel/sandybridge/pcie_config.c b/src/arch/x86/include/arch/pci_mmio_cfg.h
index 0677d766b5..dd00d376cb 100644
--- a/src/northbridge/intel/sandybridge/pcie_config.c
+++ b/src/arch/x86/include/arch/pci_mmio_cfg.h
@@ -17,7 +17,13 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#include "sandybridge.h"
+#ifndef _PCI_MMIO_CFG_H
+#define _PCI_MMIO_CFG_H
+
+#include <arch/io.h>
+
+#if CONFIG_MMCONF_SUPPORT
+#define DEFAULT_PCIEXBAR	CONFIG_MMCONF_BASE_ADDRESS
 
 static inline __attribute__ ((always_inline))
 u8 pcie_read_config8(device_t dev, unsigned int where)
@@ -87,3 +93,6 @@ void pcie_or_config32(device_t dev, unsigned int where, u32 ormask)
 	u32 value = pcie_read_config32(dev, where);
 	pcie_write_config32(dev, where, value | ormask);
 }
+
+#endif /* CONFIG_MMCONF_SUPPORT */
+#endif /* _PCI_MMIO_CFG_H */
diff --git a/src/mainboard/google/stout/mainboard_smi.c b/src/mainboard/google/stout/mainboard_smi.c
index 79810466c6..8b37da3724 100644
--- a/src/mainboard/google/stout/mainboard_smi.c
+++ b/src/mainboard/google/stout/mainboard_smi.c
@@ -24,7 +24,6 @@
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/bd82x6x/me.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
-#include <northbridge/intel/sandybridge/pcie_config.c>
 #include <cpu/intel/model_206ax/model_206ax.h>
 
 /* Include romstage serial for SIO helper functions */
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index fd9f6b79b1..946f7aa7dd 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -23,7 +23,6 @@
 #include <arch/io.h>
 #include <device/pci_def.h>
 #include "i945.h"
-#include "pcie_config.c"
 
 int i945_silicon_revision(void)
 {
diff --git a/src/northbridge/intel/i945/pcie_config.c b/src/northbridge/intel/i945/pcie_config.c
deleted file mode 100644
index 0310d67af6..0000000000
--- a/src/northbridge/intel/i945/pcie_config.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include "i945.h"
-
-static inline __attribute__ ((always_inline))
-u8 pcie_read_config8(device_t dev, unsigned int where)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	return read8(addr);
-}
-
-static inline __attribute__ ((always_inline))
-u16 pcie_read_config16(device_t dev, unsigned int where)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	return read16(addr);
-}
-
-static inline __attribute__ ((always_inline))
-u32 pcie_read_config32(device_t dev, unsigned int where)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	return read32(addr);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_write_config8(device_t dev, unsigned int where, u8 value)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	write8(addr, value);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_write_config16(device_t dev, unsigned int where, u16 value)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	write16(addr, value);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_write_config32(device_t dev, unsigned int where, u32 value)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	write32(addr, value);
-}
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index 583385b3c1..d688f5b5a1 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -25,7 +25,6 @@
 #include <device/pci_def.h>
 #include <elog.h>
 #include "sandybridge.h"
-#include "pcie_config.c"
 
 static void sandybridge_setup_bars(void)
 {
diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c
index 0fa8d1a8a4..9b41cfab2a 100644
--- a/src/northbridge/intel/sandybridge/finalize.c
+++ b/src/northbridge/intel/sandybridge/finalize.c
@@ -20,7 +20,6 @@
 
 #include <arch/io.h>
 #include <stdlib.h>
-#include "pcie_config.c"
 #include "sandybridge.h"
 
 #define PCI_DEV_SNB PCI_DEV(0, 0, 0)
diff --git a/src/northbridge/intel/sch/pcie_config.c b/src/northbridge/intel/sch/pcie_config.c
deleted file mode 100644
index ad7d746f3b..0000000000
--- a/src/northbridge/intel/sch/pcie_config.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-static inline __attribute__ ((always_inline))
-u8 pcie_read_config8(device_t dev, unsigned int where)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	return read8(addr);
-}
-
-static inline __attribute__ ((always_inline))
-u16 pcie_read_config16(device_t dev, unsigned int where)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	return read16(addr);
-}
-
-static inline __attribute__ ((always_inline))
-u32 pcie_read_config32(device_t dev, unsigned int where)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	return read32(addr);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_write_config8(device_t dev, unsigned int where, u8 value)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	write8(addr, value);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_write_config16(device_t dev, unsigned int where, u16 value)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	write16(addr, value);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_write_config32(device_t dev, unsigned int where, u32 value)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	write32(addr, value);
-}
diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c
index 331e26cab1..76e75c8240 100644
--- a/src/southbridge/intel/bd82x6x/finalize.c
+++ b/src/southbridge/intel/bd82x6x/finalize.c
@@ -20,7 +20,6 @@
 
 #include <arch/io.h>
 #include <console/post_codes.h>
-#include <northbridge/intel/sandybridge/pcie_config.c>
 #include "pch.h"
 #include <spi-generic.h>
 
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 7fdf9261f8..626e61a96a 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -38,7 +38,7 @@
 #include <elog.h>
 
 #ifdef __SMM__
-# include <northbridge/intel/sandybridge/pcie_config.c>
+#include <arch/pci_mmio_cfg.h>
 #else
 # include <device/device.h>
 # include <device/pci.h>
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index f79adf59c0..72175d81a3 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -38,7 +38,7 @@
 #include <elog.h>
 
 #ifdef __SMM__
-# include <northbridge/intel/sandybridge/pcie_config.c>
+#include <arch/pci_mmio_cfg.h>
 #else
 # include <device/device.h>
 # include <device/pci.h>
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index 591311555d..9588703c6d 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -37,7 +37,7 @@
  *  2. we don't need to worry about how we leave 0xcf8/0xcfc behind
  */
 #include <northbridge/intel/sandybridge/sandybridge.h>
-#include <northbridge/intel/sandybridge/pcie_config.c>
+#include <arch/pci_mmio_cfg.h>
 
 /* While we read PMBASE dynamically in case it changed, let's
  * initialize it with a sane value
diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c
index 09169b1bc8..c720afeed5 100644
--- a/src/southbridge/intel/bd82x6x/spi.c
+++ b/src/southbridge/intel/bd82x6x/spi.c
@@ -34,7 +34,7 @@
 #define min(a, b) ((a)<(b)?(a):(b))
 
 #ifdef __SMM__
-#include <northbridge/intel/sandybridge/pcie_config.c>
+#include <arch/pci_mmio_cfg.h>
 #define pci_read_config_byte(dev, reg, targ)\
 	*(targ) = pcie_read_config8(dev, reg)
 #define pci_read_config_word(dev, reg, targ)\
diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c
index 5470890d26..9b0c235d97 100644
--- a/src/southbridge/intel/i82801dx/smihandler.c
+++ b/src/southbridge/intel/i82801dx/smihandler.c
@@ -207,12 +207,6 @@ static void dump_tco_status(u32 tco_sts)
 	printk(BIOS_DEBUG, "\n");
 }
 
-/* We are using PCIe accesses for now
- *  1. the chipset can do it
- *  2. we don't need to worry about how we leave 0xcf8/0xcfc behind
- */
-// #include "../../../northbridge/intel/i945/pcie_config.c"
-
 int southbridge_io_trap_handler(int smif)
 {
 	switch (smif) {
diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c
index d143ce393a..03c5d0912c 100644
--- a/src/southbridge/intel/i82801gx/smihandler.c
+++ b/src/southbridge/intel/i82801gx/smihandler.c
@@ -207,7 +207,7 @@ static void dump_tco_status(u32 tco_sts)
  *  1. the chipset can do it
  *  2. we don't need to worry about how we leave 0xcf8/0xcfc behind
  */
-#include "../../../northbridge/intel/i945/pcie_config.c"
+#include <arch/pci_mmio_cfg.h>
 
 int southbridge_io_trap_handler(int smif)
 {
diff --git a/src/southbridge/intel/sch/smihandler.c b/src/southbridge/intel/sch/smihandler.c
index 2ccbc7f9ba..507413820a 100644
--- a/src/southbridge/intel/sch/smihandler.c
+++ b/src/southbridge/intel/sch/smihandler.c
@@ -229,13 +229,6 @@ static void dump_tco_status(u32 tco_sts)
 }
 #endif
 
-
-/* We are using PCIe accesses for now
- *  1. the chipset can do it
- *  2. we don't need to worry about how we leave 0xcf8/0xcfc behind
- */
-//#include "../../../northbridge/intel/i945/pcie_config.c"
-
 int southbridge_io_trap_handler(int smif)
 {
 	//global_nvs_t *gnvs = (global_nvs_t *)0xc00;