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| author | Matt DeVillier <matt.devillier@gmail.com> | 2018-01-17 19:39:52 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-03-08 18:19:28 +0000 |
| commit | 5d6ab45dbb641187f82b4e3ed7487488ccd4971c (patch) | |
| tree | 62abc9894a95b6c2805a320b46efaf14b6964a5e /src | |
| parent | 5dd4a2a4b081caa1c7b2e871067a0ac1b9bff7ed (diff) | |
| download | coreboot-5d6ab45dbb641187f82b4e3ed7487488ccd4971c.tar.xz | |
soc/intel/braswell: add resource allocation for LPE BAR1
coreboot's PCI resource allocator doesn't assign BAR1 for
Braswell's LPE device because it doesn't exist, but is
required by Windows drivers for the device to function.
Manually add the required resource via the existing
lpe_read_resources function, and marked it as IORESOURCE_STORED
so pci_dev_set_resources ignores it.
TEST: boot Windows 10 on google/edgar, observe that memory resources
are properly assigned to LPE driver for BAR1 and no error reported.
Change-Id: Iaa68319da5fb999fe8d73792eaee692cce60c8a2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/braswell/lpe.c | 29 |
1 files changed, 26 insertions, 3 deletions
diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index 8ec944bed5..436099b4d6 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -77,8 +77,7 @@ static void lpe_enable_acpi_mode(device_t dev) /* Save BAR0, BAR1, and firmware base to ACPI NVS */ assign_device_nvs(dev, &gnvs->dev.lpe_bar0, PCI_BASE_ADDRESS_0); - /* LPE seems does not have BAR at PCI_BASE_ADDRESS_1 so disable it. */ - /* assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_1); */ + assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_2); assign_device_nvs(dev, &gnvs->dev.lpe_fw, FIRMWARE_PCI_REG_BASE); /* Device is enabled in ACPI mode */ @@ -165,16 +164,40 @@ static void lpe_init(device_t dev) static void lpe_read_resources(device_t dev) { + struct resource *res; pci_dev_read_resources(dev); + /* + * Allocate the BAR1 resource at index 2 to fulfil the Windows driver + * interface requirements even though the PCI device has only one BAR + */ + res = new_resource(dev, PCI_BASE_ADDRESS_2); + res->base = 0; + res->size = 0x1000; + res->limit = 0xffffffff; + res->gran = 12; + res->align = 12; + res->flags = IORESOURCE_MEM; + reserved_ram_resource(dev, FIRMWARE_PCI_REG_BASE, FIRMWARE_PHYS_BASE >> 10, FIRMWARE_PHYS_LENGTH >> 10); } +static void lpe_set_resources(device_t dev) +{ + struct resource *res; + + res = find_resource(dev, PCI_BASE_ADDRESS_2); + if (res != NULL) + res->flags |= IORESOURCE_STORED; + + pci_dev_set_resources(dev); +} + static const struct device_operations device_ops = { .read_resources = lpe_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = lpe_set_resources, .enable_resources = pci_dev_enable_resources, .init = lpe_init, .enable = NULL, |