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| author | Stefan Reinauer <reinauer@chromium.org> | 2012-05-23 11:18:35 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-05-30 00:53:11 +0200 |
| commit | 691c9f0dab96c1d5f4bbccb0991feb39e8986746 (patch) | |
| tree | 82b3a46ed6c43c9ec5462b4c28f5781c3e05464d /src | |
| parent | 68b5da0e680b9066afa3bbff9e1ef99d2c7df720 (diff) | |
| download | coreboot-691c9f0dab96c1d5f4bbccb0991feb39e8986746.tar.xz | |
Add support for Panther Point to SPI driver
Change-Id: I98b05d9e639eda880b6e8dc6398413d1f4f5e9c3
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1048
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/include/device/pci_ids.h | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/spi.c | 29 |
2 files changed, 22 insertions, 9 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 176529344e..4ebd572256 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2504,6 +2504,8 @@ #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN 0x1c41 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX 0x1c5f +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN 0x1e41 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e5d #define PCI_DEVICE_ID_INTEL_TGP_LPC 0x27bc /* Intel 82801E (C-ICH) */ diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c index 95fbfb9af4..ccc530d884 100644 --- a/src/southbridge/intel/bd82x6x/spi.c +++ b/src/southbridge/intel/bd82x6x/spi.c @@ -286,11 +286,24 @@ void spi_free_slave(struct spi_slave *_slave) free(slave); } -static inline int spi_is_cougarpoint_lpc(uint16_t device_id) +/* + * Check if this device ID matches one of supported Intel PCH devices. + * + * Return the ICH version if there is a match, or zero otherwise. + */ +static inline int get_ich_version(uint16_t device_id) { - return device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && - device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX; -}; + if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC) + return 7; + + if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && + device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) || + (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && + device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)) + return 9; + + return 0; +} void spi_init(void) { @@ -313,11 +326,9 @@ void spi_init(void) return; } - if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC) { - ich_version = 7; - } else if (spi_is_cougarpoint_lpc(device_id)) { - ich_version = 9; - } else { + ich_version = get_ich_version(device_id); + + if (!ich_version) { printk(BIOS_DEBUG, "ICH SPI: No known ICH found.\n"); return; } |