diff options
| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2017-07-13 02:20:27 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2017-07-13 19:45:59 +0000 |
| commit | 6a00113de8b9060a7227bcfa79b3786e3e592a33 (patch) | |
| tree | 467f5653272ed2d16f6d8033ed8cd0e7391fb426 /src | |
| parent | 9f244a5494192707bfbb72e60f17411e9a35434a (diff) | |
| download | coreboot-6a00113de8b9060a7227bcfa79b3786e3e592a33.tar.xz | |
Rename __attribute__((packed)) --> __packed
Also unify __attribute__ ((..)) to __attribute__((..)) and
handle ((__packed__)) like ((packed))
Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/15921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
193 files changed, 822 insertions, 589 deletions
diff --git a/src/arch/power8/include/arch/hlt.h b/src/arch/power8/include/arch/hlt.h index 21919d230b..0fa910b6b0 100644 --- a/src/arch/power8/include/arch/hlt.h +++ b/src/arch/power8/include/arch/hlt.h @@ -11,7 +11,7 @@ * GNU General Public License for more details. */ -static inline __attribute__ ((always_inline)) void hlt(void) +static inline __attribute__((always_inline)) void hlt(void) { while (1) ; diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index f8c5b52a3d..02884c494c 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -855,7 +855,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) } #endif -unsigned long __attribute__ ((weak)) fw_cfg_acpi_tables(unsigned long start) +unsigned long __attribute__((weak)) fw_cfg_acpi_tables(unsigned long start) { return 0; } @@ -1122,7 +1122,7 @@ void acpi_save_gnvs(u32 gnvs_address) *gnvs = gnvs_address; } -__attribute__ ((weak)) int acpi_get_gpe(int gpe) +__attribute__((weak)) int acpi_get_gpe(int gpe) { return -1; /* implemented by SOC */ } diff --git a/src/arch/x86/gdt.c b/src/arch/x86/gdt.c index c81bd61cd5..baf125cf1e 100644 --- a/src/arch/x86/gdt.c +++ b/src/arch/x86/gdt.c @@ -15,6 +15,7 @@ #include <types.h> #include <string.h> +#include <compiler.h> #include <cbmem.h> #include <console/console.h> #include <cpu/x86/gdt.h> @@ -27,7 +28,7 @@ struct gdtarg { #else u32 base; #endif -} __attribute__((packed)); +} __packed; /* Copy GDT to new location and reload it. * FIXME: We only do this for BSP CPU. diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 95cd3ac8e2..13e1e9347a 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -45,6 +45,7 @@ #if !defined(__ASSEMBLER__) && !defined(__ACPI__) && !defined(__ROMCC__) #include <stdint.h> +#include <compiler.h> #include <rules.h> #include <commonlib/helpers.h> #include <device/device.h> @@ -77,7 +78,7 @@ typedef struct acpi_rsdp { u64 xsdt_address; /* Physical address of XSDT (64 bits) */ u8 ext_checksum; /* Checksum of the whole table */ u8 reserved[3]; -} __attribute__ ((packed)) acpi_rsdp_t; +} __packed acpi_rsdp_t; /* Note: ACPI 1.0 didn't have length, xsdt_address, and ext_checksum. */ /* GAS (Generic Address Structure) */ @@ -92,7 +93,7 @@ typedef struct acpi_gen_regaddr { }; u32 addrl; /* Register address, low 32 bits */ u32 addrh; /* Register address, high 32 bits */ -} __attribute__ ((packed)) acpi_addr_t; +} __packed acpi_addr_t; #define ACPI_ADDRESS_SPACE_MEMORY 0 /* System memory */ #define ACPI_ADDRESS_SPACE_IO 1 /* System I/O */ @@ -128,7 +129,7 @@ typedef struct acpi_table_header { u32 oem_revision; /* OEM revision number */ char asl_compiler_id[4]; /* ASL compiler vendor ID */ u32 asl_compiler_revision; /* ASL compiler revision number */ -} __attribute__ ((packed)) acpi_header_t; +} __packed acpi_header_t; /* A maximum number of 32 ACPI tables ought to be enough for now. */ #define MAX_ACPI_TABLES 32 @@ -137,13 +138,13 @@ typedef struct acpi_table_header { typedef struct acpi_rsdt { struct acpi_table_header header; u32 entry[MAX_ACPI_TABLES]; -} __attribute__ ((packed)) acpi_rsdt_t; +} __packed acpi_rsdt_t; /* XSDT (Extended System Description Table) */ typedef struct acpi_xsdt { struct acpi_table_header header; u64 entry[MAX_ACPI_TABLES]; -} __attribute__ ((packed)) acpi_xsdt_t; +} __packed acpi_xsdt_t; /* HPET timers */ typedef struct acpi_hpet { @@ -153,20 +154,20 @@ typedef struct acpi_hpet { u8 number; u16 min_tick; u8 attributes; -} __attribute__ ((packed)) acpi_hpet_t; +} __packed acpi_hpet_t; /* MCFG (PCI Express MMIO config space BAR description table) */ typedef struct acpi_mcfg { struct acpi_table_header header; u8 reserved[8]; -} __attribute__ ((packed)) acpi_mcfg_t; +} __packed acpi_mcfg_t; typedef struct acpi_tcpa { struct acpi_table_header header; u16 platform_class; u32 laml; u64 lasa; -} __attribute__ ((packed)) acpi_tcpa_t; +} __packed acpi_tcpa_t; typedef struct acpi_mcfg_mmconfig { u32 base_address; @@ -175,7 +176,7 @@ typedef struct acpi_mcfg_mmconfig { u8 start_bus_number; u8 end_bus_number; u8 reserved[4]; -} __attribute__ ((packed)) acpi_mcfg_mmconfig_t; +} __packed acpi_mcfg_mmconfig_t; /* SRAT (System Resource Affinity Table) */ typedef struct acpi_srat { @@ -183,7 +184,7 @@ typedef struct acpi_srat { u32 resv; u64 resv1; /* Followed by static resource allocation structure[n] */ -} __attribute__ ((packed)) acpi_srat_t; +} __packed acpi_srat_t; /* SRAT: Processor Local APIC/SAPIC Affinity Structure */ typedef struct acpi_srat_lapic { @@ -195,7 +196,7 @@ typedef struct acpi_srat_lapic { u8 local_sapic_eid; /* Local SAPIC EID */ u8 proximity_domain_31_8[3]; /* Proximity domain bits[31:8] */ u32 resv; /* TODO: Clock domain in ACPI 4.0. */ -} __attribute__ ((packed)) acpi_srat_lapic_t; +} __packed acpi_srat_lapic_t; /* SRAT: Memory Affinity Structure */ typedef struct acpi_srat_mem { @@ -212,20 +213,20 @@ typedef struct acpi_srat_mem { * other bits reserved to 0 */ u32 resv2[2]; -} __attribute__ ((packed)) acpi_srat_mem_t; +} __packed acpi_srat_mem_t; /* SLIT (System Locality Distance Information Table) */ typedef struct acpi_slit { struct acpi_table_header header; /* Followed by static resource allocation 8+byte[num*num] */ -} __attribute__ ((packed)) acpi_slit_t; +} __packed acpi_slit_t; /* MADT (Multiple APIC Description Table) */ typedef struct acpi_madt { struct acpi_table_header header; u32 lapic_addr; /* Local APIC address */ u32 flags; /* Multiple APIC flags */ -} __attribute__ ((packed)) acpi_madt_t; +} __packed acpi_madt_t; /* VFCT image header */ struct acpi_vfct_image_hdr { @@ -239,7 +240,7 @@ struct acpi_vfct_image_hdr { u32 Revision; u32 ImageLength; u8 VbiosContent; // dummy - copy VBIOS here -} __attribute__ ((packed)); +} __packed; /* VFCT (VBIOS Fetch Table) */ struct acpi_vfct { @@ -249,10 +250,10 @@ struct acpi_vfct { u32 Lib1ImageOffset; u32 Reserved[4]; struct acpi_vfct_image_hdr image_hdr; -} __attribute__ ((packed)); +} __packed; typedef struct acpi_ivrs_info { -} __attribute__ ((packed)) acpi_ivrs_info_t; +} __packed acpi_ivrs_info_t; /* IVRS IVHD (I/O Virtualization Hardware Definition Block) Type 10h */ typedef struct acpi_ivrs_ivhd { @@ -267,7 +268,7 @@ typedef struct acpi_ivrs_ivhd { uint16_t iommu_info; uint32_t iommu_feature_info; uint8_t entry[0]; -} __attribute__ ((packed)) acpi_ivrs_ivhd_t; +} __packed acpi_ivrs_ivhd_t; /* IVRS (I/O Virtualization Reporting Structure) Type 10h */ typedef struct acpi_ivrs { @@ -275,7 +276,7 @@ typedef struct acpi_ivrs { uint32_t iv_info; uint32_t reserved[2]; struct acpi_ivrs_ivhd ivhd; -} __attribute__ ((packed)) acpi_ivrs_t; +} __packed acpi_ivrs_t; enum dev_scope_type { SCOPE_PCI_ENDPOINT = 1, @@ -293,8 +294,8 @@ typedef struct dev_scope { struct { u8 dev; u8 fn; - } __attribute__((packed)) path[0]; -} __attribute__ ((packed)) dev_scope_t; + } __packed path[0]; +} __packed dev_scope_t; enum dmar_type { DMAR_DRHD = 0, @@ -319,7 +320,7 @@ typedef struct dmar_entry { u8 reserved; u16 segment; u64 bar; -} __attribute__ ((packed)) dmar_entry_t; +} __packed dmar_entry_t; typedef struct dmar_atsr_entry { u16 type; @@ -327,7 +328,7 @@ typedef struct dmar_atsr_entry { u8 flags; u8 reserved; u16 segment; -} __attribute__ ((packed)) dmar_atsr_entry_t; +} __packed dmar_atsr_entry_t; /* DMAR (DMA Remapping Reporting Structure) */ typedef struct acpi_dmar { @@ -336,7 +337,7 @@ typedef struct acpi_dmar { u8 flags; u8 reserved[10]; dmar_entry_t structure[0]; -} __attribute__ ((packed)) acpi_dmar_t; +} __packed acpi_dmar_t; /* MADT: APIC Structure Types */ /* TODO: Convert to ALLCAPS. */ @@ -363,7 +364,7 @@ typedef struct acpi_madt_lapic { u8 processor_id; /* ACPI processor ID */ u8 apic_id; /* Local APIC ID */ u32 flags; /* Local APIC flags */ -} __attribute__ ((packed)) acpi_madt_lapic_t; +} __packed acpi_madt_lapic_t; /* MADT: Local APIC NMI Structure */ typedef struct acpi_madt_lapic_nmi { @@ -372,7 +373,7 @@ typedef struct acpi_madt_lapic_nmi { u8 processor_id; /* ACPI processor ID */ u16 flags; /* MPS INTI flags */ u8 lint; /* Local APIC LINT# */ -} __attribute__ ((packed)) acpi_madt_lapic_nmi_t; +} __packed acpi_madt_lapic_nmi_t; /* MADT: I/O APIC Structure */ typedef struct acpi_madt_ioapic { @@ -382,7 +383,7 @@ typedef struct acpi_madt_ioapic { u8 reserved; u32 ioapic_addr; /* I/O APIC address */ u32 gsi_base; /* Global system interrupt base */ -} __attribute__ ((packed)) acpi_madt_ioapic_t; +} __packed acpi_madt_ioapic_t; /* MADT: Interrupt Source Override Structure */ typedef struct acpi_madt_irqoverride { @@ -392,7 +393,7 @@ typedef struct acpi_madt_irqoverride { u8 source; /* Bus-relative int. source (IRQ) */ u32 gsirq; /* Global system interrupt */ u16 flags; /* MPS INTI flags */ -} __attribute__ ((packed)) acpi_madt_irqoverride_t; +} __packed acpi_madt_irqoverride_t; /* FADT (Fixed ACPI Description Table) */ typedef struct acpi_fadt { @@ -452,7 +453,7 @@ typedef struct acpi_fadt { struct acpi_gen_regaddr x_pm_tmr_blk; struct acpi_gen_regaddr x_gpe0_blk; struct acpi_gen_regaddr x_gpe1_blk; -} __attribute__ ((packed)) acpi_fadt_t; +} __packed acpi_fadt_t; /* FADT TABLE Revision values */ #define ACPI_FADT_REV_ACPI_1_0 1 @@ -524,7 +525,7 @@ typedef struct acpi_facs { u32 x_firmware_waking_vector_h; /* X FW waking vector, high */ u8 version; /* ACPI 4.0: 2 */ u8 resv[31]; /* FIXME: 4.0: ospm_flags */ -} __attribute__ ((packed)) acpi_facs_t; +} __packed acpi_facs_t; /* FACS flags */ #define ACPI_FACS_S4BIOS_F (1 << 0) @@ -539,14 +540,14 @@ typedef struct acpi_ecdt { u32 uid; /* UID */ u8 gpe_bit; /* GPE bit */ u8 ec_id[]; /* EC ID */ -} __attribute__ ((packed)) acpi_ecdt_t; +} __packed acpi_ecdt_t; /* HEST (Hardware Error Source Table) */ typedef struct acpi_hest { struct acpi_table_header header; u32 error_source_count; /* error_source_struct(s) */ -} __attribute__ ((packed)) acpi_hest_t; +} __packed acpi_hest_t; /* Error Source Descriptors */ typedef struct acpi_hest_esd { @@ -559,7 +560,7 @@ typedef struct acpi_hest_esd { * pre-allocate for this error source. */ u32 max_section_per_record; -} __attribute__ ((packed)) acpi_hest_esd_t; +} __packed acpi_hest_esd_t; /* Hardware Error Notification */ typedef struct acpi_hest_hen { @@ -572,14 +573,14 @@ typedef struct acpi_hest_hen { u32 sw2poll_threshold_win; u32 error_threshold_val; u32 error_threshold_win; -} __attribute__ ((packed)) acpi_hest_hen_t; +} __packed acpi_hest_hen_t; typedef struct acpi_cstate { u8 ctype; u16 latency; u32 power; acpi_addr_t resource; -} __attribute__ ((packed)) acpi_cstate_t; +} __packed acpi_cstate_t; typedef struct acpi_tstate { u32 percent; @@ -587,7 +588,7 @@ typedef struct acpi_tstate { u32 latency; u32 control; u32 status; -} __attribute__ ((packed)) acpi_tstate_t; +} __packed acpi_tstate_t; unsigned long fw_cfg_acpi_tables(unsigned long start); diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index a59ac2c50b..d35e9647ab 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -432,28 +432,28 @@ void pnp_set_drq(pnp_devfn_t dev, unsigned int index, unsigned int drq) #include <device/pci_ops.h> #endif -static inline __attribute__ ((always_inline)) +static inline __attribute__((always_inline)) void pci_or_config8(device_t dev, unsigned int where, u8 ormask) { u8 value = pci_read_config8(dev, where); pci_write_config8(dev, where, value | ormask); } -static inline __attribute__ ((always_inline)) +static inline __attribute__((always_inline)) void pci_or_config16(device_t dev, unsigned int where, u16 ormask) { u16 value = pci_read_config16(dev, where); pci_write_config16(dev, where, value | ormask); } -static inline __attribute__ ((always_inline)) +static inline __attribute__((always_inline)) void pci_or_config32(device_t dev, unsigned int where, u32 ormask) { u32 value = pci_read_config32(dev, where); pci_write_config32(dev, where, value | ormask); } -static inline __attribute__ ((always_inline)) +static inline __attribute__((always_inline)) void pci_update_config8(device_t dev, int reg, u8 mask, u8 or) { u8 reg8; @@ -464,7 +464,7 @@ void pci_update_config8(device_t dev, int reg, u8 mask, u8 or) pci_write_config8(dev, reg, reg8); } -static inline __attribute__ ((always_inline)) +static inline __attribute__((always_inline)) void pci_update_config16(device_t dev, int reg, u16 mask, u16 or) { u16 reg16; @@ -475,7 +475,7 @@ void pci_update_config16(device_t dev, int reg, u16 mask, u16 or) pci_write_config16(dev, reg, reg16); } -static inline __attribute__ ((always_inline)) +static inline __attribute__((always_inline)) void pci_update_config32(device_t dev, int reg, u32 mask, u32 or) { u32 reg32; diff --git a/src/arch/x86/include/arch/pci_mmio_cfg.h b/src/arch/x86/include/arch/pci_mmio_cfg.h index 9b9f702630..efd8269ad2 100644 --- a/src/arch/x86/include/arch/pci_mmio_cfg.h +++ b/src/arch/x86/include/arch/pci_mmio_cfg.h @@ -20,7 +20,7 @@ #define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS -static inline __attribute__ ((always_inline)) +static inline __attribute__((always_inline)) u8 pci_mmio_read_config8(pci_devfn_t dev, unsigned int where) { void *addr; @@ -28,7 +28,7 @@ u8 pci_mmio_read_config8(pci_devfn_t dev, unsigned int where) return read8(addr); } -static inline __attribute__ ((always_inline)) +static inline __attribute__((always_inline)) u16 pci_mmio_read_config16(pci_devfn_t dev, unsigned int where) { void *addr; @@ -36,7 +36,7 @@ u16 pci_mmio_read_config16(pci_devfn_t dev, unsigned int where) return read16(addr); } -static inline __attribute__ ((always_inline)) +static inline __attribute__((always_inline)) u32 pci_mmio_read_config32(pci_devfn_t dev, unsigned int where) { void *addr; @@ -44,7 +44,7 @@ u32 pci_mmio_read_config32(pci_devfn_t dev, unsigned int where) return read32(addr); } -static inline __attribute__ ((always_inline)) +static inline __attribute__((always_inline)) void pci_mmio_write_config8(pci_devfn_t dev, unsigned int where, u8 value) { void *addr; @@ -52,7 +52,7 @@ void pci_mmio_write_config8(pci_devfn_t dev, unsigned int where, u8 value) write8(addr, value); } -static inline __attribute__ ((always_inline)) +static inline __attribute__((always_inline)) void pci_mmio_write_config16(pci_devfn_t dev, unsigned int where, u16 value) { void *addr; @@ -60,7 +60,7 @@ void pci_mmio_write_config16(pci_devfn_t dev, unsigned int where, u16 value) write16(addr, value); } -static inline __attribute__ ((always_inline)) +static inline __attribute__((always_inline)) void pci_mmio_write_config32(pci_devfn_t dev, unsigned int where, u32 value) { void *addr; diff --git a/src/arch/x86/include/arch/pirq_routing.h b/src/arch/x86/include/arch/pirq_routing.h index 5236b90f7e..1ca7618f14 100644 --- a/src/arch/x86/include/arch/pirq_routing.h +++ b/src/arch/x86/include/arch/pirq_routing.h @@ -28,6 +28,7 @@ #define MAX_INTX_ENTRIES 4 #include <stdint.h> +#include <compiler.h> #define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24)) #define PIRQ_VERSION 0x0100 @@ -37,10 +38,10 @@ struct irq_info { struct { u8 link; /* IRQ line ID, chipset dependent, 0=not routed */ u16 bitmap; /* Available IRQs */ - } __attribute__((packed)) irq[4]; + } __packed irq[4]; u8 slot; /* Slot number, 0=onboard */ u8 rfu; -} __attribute__((packed)); +} __packed; struct irq_routing_table { u32 signature; /* PIRQ_SIGNATURE should be here */ @@ -53,7 +54,7 @@ struct irq_routing_table { u8 rfu[11]; u8 checksum; /* Modulo 256 checksum must give zero */ struct irq_info slots[CONFIG_IRQ_SLOT_COUNT]; -} __attribute__((packed)); +} __packed; unsigned long copy_pirq_routing_table(unsigned long addr, const struct irq_routing_table *routing_table); diff --git a/src/arch/x86/include/arch/registers.h b/src/arch/x86/include/arch/registers.h index 2ffcafb0a9..76fda2851d 100644 --- a/src/arch/x86/include/arch/registers.h +++ b/src/arch/x86/include/arch/registers.h @@ -16,7 +16,7 @@ #ifndef __ARCH_REGISTERS_H #define __ARCH_REGISTERS_H -#define __PACKED __attribute__((packed)) +#include <compiler.h> #define DOWNTO8(A) \ union { \ @@ -25,22 +25,22 @@ struct { \ uint8_t A##l; \ uint8_t A##h; \ - } __PACKED; \ + } __packed; \ uint16_t A##x; \ - } __PACKED; \ + } __packed; \ uint16_t h##A##x; \ - } __PACKED; \ + } __packed; \ uint32_t e##A##x; \ - } __PACKED; + } __packed; #define DOWNTO16(A) \ union { \ struct { \ uint16_t A; \ uint16_t h##A; \ - } __PACKED; \ + } __packed; \ uint32_t e##A; \ - } __PACKED; + } __packed; struct eregs { DOWNTO8(a); diff --git a/src/arch/x86/include/arch/smp/mpspec.h b/src/arch/x86/include/arch/smp/mpspec.h index 4c80dbb45a..8b3e8bb8f9 100644 --- a/src/arch/x86/include/arch/smp/mpspec.h +++ b/src/arch/x86/include/arch/smp/mpspec.h @@ -16,6 +16,7 @@ #ifndef __ASM_MPSPEC_H #define __ASM_MPSPEC_H +#include <compiler.h> #include <device/device.h> #include <cpu/x86/lapic_def.h> @@ -52,7 +53,7 @@ struct intel_mp_floating { u8 mpf_feature3; /* Unused (0) */ u8 mpf_feature4; /* Unused (0) */ u8 mpf_feature5; /* Unused (0) */ -} __attribute__((packed)); +} __packed; struct mp_config_table { char mpc_signature[4]; @@ -69,7 +70,7 @@ struct mp_config_table { u16 mpe_length; /* Extended Table size */ u8 mpe_checksum; /* Extended Table checksum */ u8 reserved; -} __attribute__((packed)); +} __packed; /* Followed by entries */ @@ -92,13 +93,13 @@ struct mpc_config_processor { #define MPC_CPU_FAMILY_MASK 0xF00 u32 mpc_featureflag; /* CPUID feature value */ u32 mpc_reserved[2]; -} __attribute__((packed)); +} __packed; struct mpc_config_bus { u8 mpc_type; u8 mpc_busid; u8 mpc_bustype[6]; -} __attribute__((packed)); +} __packed; #define BUSTYPE_EISA "EISA" #define BUSTYPE_ISA "ISA" @@ -115,7 +116,7 @@ struct mpc_config_ioapic { u8 mpc_flags; #define MPC_APIC_USABLE 0x01 void *mpc_apicaddr; -} __attribute__((packed)); +} __packed; struct mpc_config_intsrc { u8 mpc_type; @@ -125,7 +126,7 @@ struct mpc_config_intsrc { u8 mpc_srcbusirq; u8 mpc_dstapic; u8 mpc_dstirq; -} __attribute__((packed)); +} __packed; enum mp_irq_source_types { mp_INT = 0, @@ -153,7 +154,7 @@ struct mpc_config_lintsrc { u8 mpc_destapic; #define MP_APIC_ALL 0xFF u8 mpc_destapiclint; -} __attribute__((packed)); +} __packed; /* * Default configurations @@ -185,7 +186,7 @@ enum mp_bustype { struct mp_exten_config { u8 mpe_type; u8 mpe_length; -} __attribute__((packed)); +} __packed; typedef struct mp_exten_config *mpe_t; @@ -201,7 +202,7 @@ struct mp_exten_system_address_space { u32 mpe_address_base_high; u32 mpe_address_length_low; u32 mpe_address_length_high; -} __attribute__((packed)); +} __packed; struct mp_exten_bus_hierarchy { u8 mpe_type; @@ -211,7 +212,7 @@ struct mp_exten_bus_hierarchy { #define BUS_SUBTRACTIVE_DECODE 1 u8 mpe_parent_busid; u8 reserved[3]; -} __attribute__((packed)); +} __packed; struct mp_exten_compatibility_address_space { u8 mpe_type; @@ -237,7 +238,7 @@ struct mp_exten_compatibility_address_space { * XFB0 - XFBB * XFC0 - XCDF */ -} __attribute__((packed)); +} __packed; void mptable_init(struct mp_config_table *mc, u32 lapic_addr); void *smp_next_mpc_entry(struct mp_config_table *mc); diff --git a/src/commonlib/fsp_relocate.c b/src/commonlib/fsp_relocate.c index fd5a348c16..d96edd2178 100644 --- a/src/commonlib/fsp_relocate.c +++ b/src/commonlib/fsp_relocate.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <compiler.h> #include <console/console.h> #include <commonlib/endian.h> #include <commonlib/fsp.h> @@ -67,7 +68,7 @@ struct fsp_patch_table { uint8_t reserved; uint32_t patch_entry_num; uint32_t patch_entries[0]; -} __attribute__((packed)); +} __packed; #define FSPP_SIG 0x50505346 diff --git a/src/commonlib/include/commonlib/cbfs_serialized.h b/src/commonlib/include/commonlib/cbfs_serialized.h index 706f175268..9273b35958 100644 --- a/src/commonlib/include/commonlib/cbfs_serialized.h +++ b/src/commonlib/include/commonlib/cbfs_serialized.h @@ -48,6 +48,7 @@ #define _CBFS_SERIALIZED_H_ #include <stdint.h> +#include <compiler.h> /** These are standard values for the known compression algorithms that coreboot knows about for stages and @@ -101,7 +102,7 @@ struct cbfs_header { uint32_t offset; uint32_t architecture; uint32_t pad[1]; -} __attribute__((packed)); +} __packed; /* this used to be flexible, but wasn't ever set to something different. */ #define CBFS_ALIGNMENT 64 @@ -136,7 +137,7 @@ struct cbfs_file { uint32_t type; uint32_t attributes_offset; uint32_t offset; -} __attribute__((packed)); +} __packed; /* The common fields of extended cbfs file attributes. Attributes are expected to start with tag/len, then append their @@ -146,7 +147,7 @@ struct cbfs_file_attribute { /* len covers the whole structure, incl. tag and len */ uint32_t len; uint8_t data[0]; -} __attribute__((packed)); +} __packed; /* Depending on how the header was initialized, it may be backed with 0x00 or * 0xff. Support both. */ @@ -163,7 +164,7 @@ struct cbfs_file_attr_compression { /* whole file compression format. 0 if no compression. */ uint32_t compression; uint32_t decompressed_size; -} __attribute__((packed)); +} __packed; struct cbfs_file_attr_hash { uint32_t tag; @@ -171,19 +172,19 @@ struct cbfs_file_attr_hash { uint32_t hash_type; /* hash_data is len - sizeof(struct) bytes */ uint8_t hash_data[]; -} __attribute__((packed)); +} __packed; struct cbfs_file_attr_position { uint32_t tag; uint32_t len; uint32_t position; -} __attribute__((packed)); +} __packed; struct cbfs_file_attr_align { uint32_t tag; uint32_t len; uint32_t alignment; -} __attribute__((packed)); +} __packed; /* * ROMCC does not understand uint64_t, so we hide future definitions as they are @@ -205,7 +206,7 @@ struct cbfs_stage { uint64_t load; /** Where to load in memory */ uint32_t len; /** length of data to load */ uint32_t memlen; /** total length of object in memory */ -} __attribute__((packed)); +} __packed; /** this is the sub-header for payload components. Payloads are loaded by coreboot at the end of the boot process */ @@ -217,7 +218,7 @@ struct cbfs_payload_segment { uint64_t load_addr; uint32_t len; uint32_t mem_len; -} __attribute__((packed)); +} __packed; struct cbfs_payload { struct cbfs_payload_segment segments; @@ -232,7 +233,7 @@ struct cbfs_payload { struct cbfs_optionrom { uint32_t compression; uint32_t len; -} __attribute__((packed)); +} __packed; #endif /* __ROMCC__ */ diff --git a/src/commonlib/include/commonlib/fmap_serialized.h b/src/commonlib/include/commonlib/fmap_serialized.h index 3585f0bc84..cea231b2c2 100644 --- a/src/commonlib/include/commonlib/fmap_serialized.h +++ b/src/commonlib/include/commonlib/fmap_serialized.h @@ -37,6 +37,7 @@ #define FLASHMAP_SERIALIZED_H__ #include <stdint.h> +#include <compiler.h> #define FMAP_SIGNATURE "__FMAP__" #define FMAP_VER_MAJOR 1 /* this header's FMAP minor version */ @@ -56,7 +57,7 @@ struct fmap_area { uint32_t size; /* size in bytes */ uint8_t name[FMAP_STRLEN]; /* descriptive name */ uint16_t flags; /* flags for this area */ -} __attribute__((packed)); +} __packed; struct fmap { uint8_t signature[8]; /* "__FMAP__" (0x5F5F464D41505F5F) */ @@ -68,6 +69,6 @@ struct fmap { uint16_t nareas; /* number of areas described by fmap_areas[] below */ struct fmap_area areas[]; -} __attribute__((packed)); +} __packed; #endif /* FLASHMAP_SERIALIZED_H__ */ diff --git a/src/commonlib/include/commonlib/rmodule-defs.h b/src/commonlib/include/commonlib/rmodule-defs.h index 0922c811fd..485d6383bf 100644 --- a/src/commonlib/include/commonlib/rmodule-defs.h +++ b/src/commonlib/include/commonlib/rmodule-defs.h @@ -17,6 +17,7 @@ #include <stdint.h> #include <stddef.h> +#include <compiler.h> #define RMODULE_MAGIC 0xf8fe #define RMODULE_VERSION_1 1 @@ -54,6 +55,6 @@ struct rmodule_header { uint32_t bss_end; /* Add some room for growth. */ uint32_t padding[4]; -} __attribute__ ((packed)); +} __packed; #endif /* RMODULE_DEFS_H */ diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index ee5cd6f6e0..60feffed87 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -17,11 +17,12 @@ #define __TIMESTAMP_SERIALIZED_H__ #include <stdint.h> +#include <compiler.h> struct timestamp_entry { uint32_t entry_id; uint64_t entry_stamp; -} __attribute__((packed)); +} __packed; struct timestamp_table { uint64_t base_time; @@ -29,7 +30,7 @@ struct timestamp_table { uint16_t tick_freq_mhz; uint32_t num_entries; struct timestamp_entry entries[0]; /* Variable number of entries */ -} __attribute__((packed)); +} __packed; enum timestamp_id { TS_START_ROMSTAGE = 1, diff --git a/src/commonlib/lz4_wrapper.c b/src/commonlib/lz4_wrapper.c index 98f2533cab..4050ac9bb3 100644 --- a/src/commonlib/lz4_wrapper.c +++ b/src/commonlib/lz4_wrapper.c @@ -34,6 +34,7 @@ #include <commonlib/helpers.h> #include <stdint.h> #include <string.h> +#include <compiler.h> /* LZ4 comes with its own supposedly portable memory access functions, but they * seem to be very inefficient in practice (at least on ARM64). Since coreboot @@ -115,7 +116,7 @@ struct lz4_frame_header { }; /* + uint64_t content_size iff has_content_size is set */ /* + uint8_t header_checksum */ -} __attribute__((packed)); +} __packed; struct lz4_block_header { union { @@ -127,7 +128,7 @@ struct lz4_block_header { }; /* + size bytes of data */ /* + uint32_t block_checksum iff has_block_checksum is set */ -} __attribute__((packed)); +} __packed; size_t ulz4fn(const void *src, size_t srcn, void *dst, size_t dstn) { diff --git a/src/cpu/allwinner/a10/clock.h b/src/cpu/allwinner/a10/clock.h index 31bfc66041..815a94d139 100644 --- a/src/cpu/allwinner/a10/clock.h +++ b/src/cpu/allwinner/a10/clock.h @@ -23,6 +23,7 @@ #include "memmap.h" #include <types.h> +#include <compiler.h> /* CPU_AHB_APB0 config values */ #define CPU_CLK_SRC_MASK (3 << 16) @@ -267,7 +268,7 @@ struct a10_ccm { u32 mali_clk_cfg; /* 0x154 */ u8 res7[0x4]; u32 mbus_clk_cfg; /* 0x15c */ -} __attribute__ ((packed)); +} __packed; void a1x_periph_clock_enable(enum a1x_clken periph); void a1x_periph_clock_disable(enum a1x_clken periph); diff --git a/src/cpu/allwinner/a10/gpio.h b/src/cpu/allwinner/a10/gpio.h index 8d95074d63..a126801000 100644 --- a/src/cpu/allwinner/a10/gpio.h +++ b/src/cpu/allwinner/a10/gpio.h @@ -19,6 +19,7 @@ #define __CPU_ALLWINNER_A10_PINMUX_H #include <types.h> +#include <compiler.h> #define GPIO_BASE 0x01C20800 @@ -42,7 +43,7 @@ struct a10_gpio_port { u32 dat; u32 drv[2]; u32 pul[2]; -} __attribute__ ((packed)); +} __packed; struct a10_gpio { struct a10_gpio_port port[10]; @@ -58,7 +59,7 @@ struct a10_gpio { u32 sdr_pad_drv; u32 sdr_pad_pul; -} __attribute__ ((packed)); +} __packed; /* gpio.c */ void gpio_set(u8 port, u8 pin); diff --git a/src/cpu/allwinner/a10/timer.h b/src/cpu/allwinner/a10/timer.h index 7e10f2f2dd..e24bf6618b 100644 --- a/src/cpu/allwinner/a10/timer.h +++ b/src/cpu/allwinner/a10/timer.h @@ -23,6 +23,7 @@ #include "memmap.h" #include <types.h> +#include <compiler.h> /* TMRx_CTRL values */ #define TIMER_CTRL_MODE_SINGLE (1 << 7) @@ -48,7 +49,7 @@ struct a1x_timer { u32 interval; u32 val; u8 res[4]; -} __attribute__ ((packed)); +} __packed; /* Audio video sync*/ struct a1x_avs { @@ -56,27 +57,27 @@ struct a1x_avs { u32 cnt0; /* 0x84 */ u32 cnt1; /* 0x88 */ u32 div; /* 0x8c */ -} __attribute__ ((packed)); +} __packed; /* Watchdog */ struct a1x_wdog { u32 ctrl; /* 0x90 */ u32 mode; /* 0x94 */ -} __attribute__ ((packed)); +} __packed; /* 64 bit counter */ struct a1x_64cnt { u32 ctrl; /* 0xa0 */ u32 lo; /* 0xa4 */ u32 hi; /* 0xa8 */ -} __attribute__ ((packed)); +} __packed; /* Rtc */ struct a1x_rtc { u32 ctrl; /* 0x100 */ u32 yymmdd; /* 0x104 */ u32 hhmmss; /* 0x108 */ -} __attribute__ ((packed)); +} __packed; /* Alarm */ struct a1x_alarm { @@ -85,7 +86,7 @@ struct a1x_alarm { u32 en; /* 0x114 */ u32 irq_en; /* 0x118 */ u32 irq_sta; /* 0x11c */ -} __attribute__ ((packed)); +} __packed; struct a1x_timer_module { u32 irq_en; /* 0x00 */ @@ -103,7 +104,7 @@ struct a1x_timer_module { u32 gp_data[4]; u8 res5[8]; u32 cpu_cfg; -} __attribute__ ((packed)); +} __packed; u8 a1x_get_cpu_chip_revision(void); diff --git a/src/cpu/allwinner/a10/uart.h b/src/cpu/allwinner/a10/uart.h index a5ed2a9f70..92a87e5d11 100644 --- a/src/cpu/allwinner/a10/uart.h +++ b/src/cpu/allwinner/a10/uart.h @@ -26,6 +26,7 @@ #define CPU_ALLWINNER_A10_UART_H #include <types.h> +#include <compiler.h> struct a10_uart { union { @@ -71,7 +72,7 @@ struct a10_uart { u8 reserved_0xa0[4]; u32 halt; /* Halt register */ -} __attribute__ ((packed)); +} __packed; enum uart_parity { UART_PARITY_NONE, diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index c151aac5d1..f5a949cede 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -231,7 +231,7 @@ static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue) static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid); #endif -static inline __attribute__ ((always_inline)) +static inline __attribute__((always_inline)) void print_apicid_nodeid_coreid(u32 apicid, struct node_core_id id, const char *str) { diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 48920bba6f..fce67acab5 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -144,7 +144,7 @@ static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue) static void init_fidvid_ap(u32 bsp_apicid, u32 apicid); #endif -static inline __attribute__ ((always_inline)) +static inline __attribute__((always_inline)) void print_apicid_nodeid_coreid(u32 apicid, struct node_core_id id, const char *str) { diff --git a/src/cpu/amd/model_fxx/microcode_blob.c b/src/cpu/amd/model_fxx/microcode_blob.c index 98b418b84b..2dded4af32 100644 --- a/src/cpu/amd/model_fxx/microcode_blob.c +++ b/src/cpu/amd/model_fxx/microcode_blob.c @@ -11,7 +11,7 @@ * GNU General Public License for more details. */ -unsigned char microcode[] __attribute__ ((aligned(16))) = { +unsigned char microcode[] __attribute__((aligned(16))) = { #if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) #include "../../../../3rdparty/blobs/cpu/amd/model_fxx/microcode.h" #endif diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index 387fb8ba25..a349594fa6 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -18,6 +18,7 @@ #include <types.h> #include <string.h> +#include <compiler.h> #include <device/device.h> #include <device/pci.h> #include <cpu/cpu.h> @@ -40,7 +41,7 @@ struct ied_header { char signature[10]; u32 size; u8 reserved[34]; -} __attribute__ ((packed)); +} __packed; struct smm_relocation_params { diff --git a/src/cpu/ti/am335x/clock.h b/src/cpu/ti/am335x/clock.h index c1f1926852..564838a0e4 100644 --- a/src/cpu/ti/am335x/clock.h +++ b/src/cpu/ti/am335x/clock.h @@ -16,6 +16,7 @@ #define __CPU_TI_AM335X_CLOCK_H__ #include <stdint.h> +#include <compiler.h> enum { CM_ST_NO_SLEEP = 0x0, @@ -106,7 +107,7 @@ struct am335x_cm_per_regs { uint32_t lcdc_st; // 0x148 uint32_t clkdiv32k; // 0x14c uint32_t clk_24mhz_st; // 0x150 -} __attribute__((packed)); +} __packed; static struct am335x_cm_per_regs * const am335x_cm_per = (void *)0x44e00000; /* Clock module wakeup registers */ @@ -166,7 +167,7 @@ struct am335x_cm_wkup_regs { uint8_t _rsv0[4]; // 0xd0-0xd3 uint32_t wkup_wdt1; // 0xd4 uint32_t div_m6_dpll_core; // 0xd8 -} __attribute__((packed)); +} __packed; static struct am335x_cm_wkup_regs * const am335x_cm_wkup = (void *)0x44e00400; /* Clock module pll registers */ @@ -187,20 +188,20 @@ struct am335x_cm_dpll_regs { uint32_t clksel_lcdc_pixel_clk; // 0x34 uint32_t clksel_wdt1_clk; // 0x38 uint32_t clksel_gpio0_dbclk; // 0x3c -} __attribute__((packed)); +} __packed; static struct am335x_cm_dpll_regs * const am335x_cm_dpll = (void *)0x44e00500; /* Clock module mpu registers */ struct am335x_cm_mpu_regs { uint32_t st; // 0x0 uint32_t mpu; // 0x4 -} __attribute__((packed)); +} __packed; static struct am335x_cm_mpu_regs * const am335x_cm_mpu = (void *)0x44e00600; /* Clock module device registers */ struct am335x_cm_device_regs { uint32_t cm_clkout_ctrl; // 0x0 -} __attribute__((packed)); +} __packed; static struct am335x_cm_device_regs * const am335x_cm_device = (void *)0x44e00700; @@ -208,7 +209,7 @@ static struct am335x_cm_device_regs * const am335x_cm_device = struct am335x_cm_rtc_regs { uint32_t rtc; // 0x0 uint32_t st; // 0x4 -} __attribute__((packed)); +} __packed; static struct am335x_cm_rtc_regs * const am335x_cm_rtc = (void *)0x44e00800; /* Clock module graphics controller registers */ @@ -219,7 +220,7 @@ struct am335x_cm_gfx_regs { uint32_t l4ls_gfx_st; // 0xc uint32_t mmucfg; // 0x10 uint32_t mmudata; // 0x14 -} __attribute__((packed)); +} __packed; static struct am335x_cm_gfx_regs * const am335x_cm_gfx = (void *)0x44e00900; /* Clock module efuse registers */ @@ -227,7 +228,7 @@ struct am335x_cm_cefuse_regs { uint32_t st; // 0x0 uint8_t _rsv0[0x1c]; // 0x4-0x1f uint32_t cefuse; // 0x20 -} __attribute__((packed)); +} __packed; static struct am335x_cm_cefuse_regs * const am335x_cm_cefuse = (void *)0x44e00a00; diff --git a/src/cpu/ti/am335x/gpio.h b/src/cpu/ti/am335x/gpio.h index 4f4e635202..41fc3d358e 100644 --- a/src/cpu/ti/am335x/gpio.h +++ b/src/cpu/ti/am335x/gpio.h @@ -16,6 +16,7 @@ #define __CPU_TI_AM335X_GPIO_H__ #include <stdint.h> +#include <compiler.h> enum { AM335X_GPIO_BITS_PER_BANK = 32 @@ -53,7 +54,7 @@ struct am335x_gpio_regs { uint8_t _rsv4[0x38]; // 0x158-0x18f uint32_t cleardataout; // 0x190 uint32_t setdataout; // 0x194 -} __attribute__((packed)); +} __packed; static struct am335x_gpio_regs * const am335x_gpio_banks[] = { (void *)0x44e07000, (void *)0x4804c000, diff --git a/src/cpu/ti/am335x/header.c b/src/cpu/ti/am335x/header.c index d59e29749d..a260425f48 100644 --- a/src/cpu/ti/am335x/header.c +++ b/src/cpu/ti/am335x/header.c @@ -15,6 +15,7 @@ #include <stddef.h> #include <stdint.h> #include <symbols.h> +#include <compiler.h> #include "header.h" @@ -25,7 +26,7 @@ struct config_headers { // An inert instance of chsettings. struct configuration_header_settings chsettings; -} __attribute__((packed)); +} __packed; struct omap_image_headers { union { diff --git a/src/cpu/ti/am335x/header.h b/src/cpu/ti/am335x/header.h index 43a628065a..64d75c7512 100644 --- a/src/cpu/ti/am335x/header.h +++ b/src/cpu/ti/am335x/header.h @@ -16,6 +16,7 @@ #define __CPU_TI_AM335X_HEADER_H #include <stdint.h> +#include <compiler.h> struct configuration_header_toc_item { // Offset from the start address of the TOC to the actual address of @@ -30,7 +31,7 @@ struct configuration_header_toc_item { // 12-character name of a section, including the zero (\0) terminator. char filename[12]; -} __attribute__((packed)); +} __packed; struct configuration_header_settings { // Key used for section verification. @@ -49,7 +50,7 @@ struct configuration_header_settings { // Flags. It's not clear what this is used for. uint32_t flags; -} __attribute__((packed)); +} __packed; struct gp_device_header { // Size of the image. @@ -57,6 +58,6 @@ struct gp_device_header { // Address to store the image/code entry point. uint32_t destination; -} __attribute__((packed)); +} __packed; #endif diff --git a/src/cpu/ti/am335x/uart.h b/src/cpu/ti/am335x/uart.h index 07c7cc8987..7a65076b10 100644 --- a/src/cpu/ti/am335x/uart.h +++ b/src/cpu/ti/am335x/uart.h @@ -15,6 +15,8 @@ #ifndef AM335X_UART_H #define AM335X_UART_H +#include <compiler.h> + #define AM335X_UART0_BASE 0x44e09000 #define AM335X_UART1_BASE 0x48020000 #define AM335X_UART2_BASE 0x48024000 @@ -168,6 +170,6 @@ struct am335x_uart { uint8_t rsvd_0x82[2]; uint16_t txdma; /* TX DMA threshold */ -} __attribute__((packed)); +} __packed; #endif /* AM335X_UART_H */ diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index c03efe9455..4eb9519c7c 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -16,6 +16,7 @@ #include <console/console.h> #include <stdint.h> +#include <compiler.h> #include <rmodule.h> #include <arch/cpu.h> #include <cpu/cpu.h> @@ -103,14 +104,14 @@ struct sipi_params { uint32_t msr_count; uint32_t c_handler; atomic_t ap_count; -} __attribute__((packed)); +} __packed; /* This also needs to match the assembly code for saved MSR encoding. */ struct saved_msr { uint32_t index; uint32_t lo; uint32_t hi; -} __attribute__((packed)); +} __packed; /* The sipi vector rmodule is included in the ramstage using 'objdump -B'. */ diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index 1ff9371b98..3532e9781e 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <compiler.h> #include <console/console.h> #include <cpu/cpu.h> #include <cpu/x86/pae.h> @@ -59,14 +60,14 @@ void *map_2M_page(unsigned long page) struct pde { uint32_t addr_lo; uint32_t addr_hi; - } __attribute__ ((packed)); + } __packed; struct pg_table { struct pde pd[2048]; struct pde pdp[512]; - } __attribute__ ((packed)); + } __packed; static struct pg_table pgtbl[CONFIG_MAX_CPUS] - __attribute__ ((aligned(4096))); + __attribute__((aligned(4096))); static unsigned long mapped_window[CONFIG_MAX_CPUS]; unsigned long index; unsigned long window; diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index 16415baac1..6999f566e2 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -28,7 +28,7 @@ static int do_driver_init = 1; typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore; /* SMI multiprocessing semaphore */ -static __attribute__ ((aligned(4))) volatile smi_semaphore smi_handler_status +static __attribute__((aligned(4))) volatile smi_semaphore smi_handler_status = SMI_UNLOCKED; static int smi_obtain_lock(void) diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index 4bcd853b9a..cfb2b91668 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -28,7 +28,7 @@ typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore; /* SMI multiprocessing semaphore */ static volatile -__attribute__ ((aligned(4))) smi_semaphore smi_handler_status = SMI_UNLOCKED; +__attribute__((aligned(4))) smi_semaphore smi_handler_status = SMI_UNLOCKED; static int smi_obtain_lock(void) { diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index b7de178bd9..3d7952ff42 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <compiler.h> #include <string.h> #include <rmodule.h> #include <cpu/x86/smm.h> @@ -47,7 +48,7 @@ struct smm_stub_params { u32 fxsave_area; u32 fxsave_area_size; struct smm_runtime runtime; -} __attribute__ ((packed)); +} __packed; /* * The stub is the entry point that sets up protected mode and stacks for each @@ -67,7 +68,7 @@ extern unsigned char _binary_smmstub_start[]; struct smm_entry_ins { char jmp_rel; uint16_t rel16; -} __attribute__ ((packed)); +} __packed; /* * Place the entry instructions for num entries beginning at entry_start with diff --git a/src/device/oprom/yabel/device.c b/src/device/oprom/yabel/device.c index b3e5d19fdf..cd1abfb026 100644 --- a/src/device/oprom/yabel/device.c +++ b/src/device/oprom/yabel/device.c @@ -33,6 +33,7 @@ *****************************************************************************/ +#include <compiler.h> #include "device.h" #include "compat/rtas.h" #include <string.h> @@ -56,7 +57,7 @@ typedef struct { u8 cfg_space_offset; u64 address; u64 size; -} __attribute__ ((__packed__)) assigned_address_t; +} __packed assigned_address_t; #if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) /* coreboot version */ diff --git a/src/device/oprom/yabel/device.h b/src/device/oprom/yabel/device.h index 98b5c07833..1028ef1833 100644 --- a/src/device/oprom/yabel/device.h +++ b/src/device/oprom/yabel/device.h @@ -36,6 +36,7 @@ #define DEVICE_LIB_H #include <types.h> +#include <compiler.h> #include <endian.h> #include "compat/of.h" #include "debug.h" @@ -62,7 +63,7 @@ typedef struct { u16 bev; // Bootstrap Entry Vector u16 reserved_2; u16 sriv; // Static Resource Information Vector -} __attribute__ ((__packed__)) exp_header_struct_t; +} __packed exp_header_struct_t; // a PCI Data Struct as defined in PCI 2.3 Spec Chapter 6.3.1.2 typedef struct { @@ -78,7 +79,7 @@ typedef struct { u8 code_type; u8 indicator; u16 reserved_2; -} __attribute__ ((__packed__)) pci_data_struct_t; +} __packed pci_data_struct_t; typedef struct { u8 bus; @@ -116,7 +117,7 @@ typedef struct { u64 address; u64 address_offset; u64 size; -} __attribute__ ((__packed__)) translate_address_t; +} __packed translate_address_t; // array to store address translations for this // device. Needed for faster address translation, so diff --git a/src/device/oprom/yabel/pmm.h b/src/device/oprom/yabel/pmm.h index c3abee36d5..3c96700e16 100644 --- a/src/device/oprom/yabel/pmm.h +++ b/src/device/oprom/yabel/pmm.h @@ -35,6 +35,7 @@ #define _YABEL_PMM_H_ #include <types.h> +#include <compiler.h> /* PMM Structure see PMM Spec Version 1.01 Chapter 3.1.1 * (search web for specspmm101.pdf) @@ -54,7 +55,7 @@ typedef struct { * see interrupt.c) and the INT Handler will do the actual PMM work. */ u8 code[3]; -} __attribute__ ((__packed__)) pmm_information_t; +} __packed pmm_information_t; /* This function is used to setup the PMM struct in virtual memory * at a certain offset */ diff --git a/src/drivers/elog/boot_count.c b/src/drivers/elog/boot_count.c index 9d717d8888..6e9fcaba3a 100644 --- a/src/drivers/elog/boot_count.c +++ b/src/drivers/elog/boot_count.c @@ -18,6 +18,7 @@ #include <pc80/mc146818rtc.h> #include <stddef.h> #include <stdint.h> +#include <compiler.h> #include <elog.h> /* @@ -43,7 +44,7 @@ struct boot_count { u16 signature; u32 count; u16 checksum; -} __attribute__ ((packed)); +} __packed; /* Read and validate boot count structure from CMOS */ static int boot_count_cmos_read(struct boot_count *bc) diff --git a/src/drivers/elog/elog_internal.h b/src/drivers/elog/elog_internal.h index a09bbefe8d..3ccee90c46 100644 --- a/src/drivers/elog/elog_internal.h +++ b/src/drivers/elog/elog_internal.h @@ -16,13 +16,14 @@ #ifndef ELOG_INTERNAL_H_ #define ELOG_INTERNAL_H_ +#include <compiler.h> /* ELOG header */ struct elog_header { u32 magic; u8 version; u8 header_size; u8 reserved[2]; -} __attribute__ ((packed)); +} __packed; /* ELOG related constants */ #define ELOG_SIGNATURE 0x474f4c45 /* 'ELOG' */ @@ -40,7 +41,7 @@ struct event_header { u8 hour; u8 minute; u8 second; -} __attribute__ ((packed)); +} __packed; /* SMBIOS Type 15 related constants */ #define ELOG_HEADER_TYPE_OEM 0x88 diff --git a/src/drivers/elog/gsmi.c b/src/drivers/elog/gsmi.c index f125d237fb..cd94cf61b6 100644 --- a/src/drivers/elog/gsmi.c +++ b/src/drivers/elog/gsmi.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <compiler.h> #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> @@ -33,17 +34,17 @@ struct gsmi_set_eventlog_param { u32 data_ptr; u32 data_len; u32 type; -} __attribute__ ((packed)); +} __packed; struct gsmi_set_eventlog_type1 { u16 type; u32 instance; -} __attribute__ ((packed)); +} __packed; struct gsmi_clear_eventlog_param { u32 percentage; u32 data_type; -} __attribute__ ((packed)); +} __packed; /* Param is usually EBX, ret in EAX */ u32 gsmi_exec(u8 command, u32 *param) diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c index aa59f1e917..3505dcec1d 100644 --- a/src/drivers/i2c/tpm/cr50.c +++ b/src/drivers/i2c/tpm/cr50.c @@ -57,7 +57,7 @@ struct tpm_inf_dev { static struct tpm_inf_dev g_tpm_dev CAR_GLOBAL; -__attribute__ ((weak)) int tis_plat_irq_status(void) +__attribute__((weak)) int tis_plat_irq_status(void) { static int warning_displayed CAR_GLOBAL; diff --git a/src/drivers/i2c/tpm/tis_atmel.c b/src/drivers/i2c/tpm/tis_atmel.c index 7d8b7a17b8..b6e13513f3 100644 --- a/src/drivers/i2c/tpm/tis_atmel.c +++ b/src/drivers/i2c/tpm/tis_atmel.c @@ -14,6 +14,7 @@ #include <arch/early_variables.h> #include <stdint.h> +#include <compiler.h> #include <string.h> #include <assert.h> #include <commonlib/endian.h> @@ -33,7 +34,7 @@ struct tpm_output_header { uint16_t tag; uint32_t length; uint32_t return_code; -} __attribute__ ((packed)); +} __packed; int tis_open(void) { diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c index b43f0df100..fc1bd51161 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.c +++ b/src/drivers/intel/fsp1_0/fsp_util.c @@ -66,7 +66,7 @@ void FspNotify (u32 Phase) * Call the FSP to do memory init. The FSP doesn't return to this function. * The FSP returns to the romstage_main_continue(). */ -void __attribute__ ((noreturn)) fsp_early_init (FSP_INFO_HEADER *fsp_ptr) +void __attribute__((noreturn)) fsp_early_init (FSP_INFO_HEADER *fsp_ptr) { FSP_FSP_INIT FspInitApi; FSP_INIT_PARAMS FspInitParams; diff --git a/src/drivers/intel/fsp1_0/fsp_util.h b/src/drivers/intel/fsp1_0/fsp_util.h index bbdd4de148..badd254f80 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.h +++ b/src/drivers/intel/fsp1_0/fsp_util.h @@ -16,6 +16,7 @@ #ifndef FSP_UTIL_H #define FSP_UTIL_H +#include <compiler.h> #include <chipset_fsp_util.h> #include "fsp_values.h" @@ -71,7 +72,7 @@ struct mrc_data_container { u32 mrc_checksum; // IP style checksum u32 reserved; // For header alignment u8 mrc_data[0]; // Variable size, platform/run time dependent. -} __attribute__ ((packed)); +} __packed; struct mrc_data_container *find_current_mrc_cache(void); diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index 8b23c4a388..34d6e4881d 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <compiler.h> #include <bootstate.h> #include <cbmem.h> #include <console/console.h> @@ -185,7 +186,7 @@ BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, struct fsp_runtime { uint32_t fih; uint32_t hob_list; -} __attribute__((packed)); +} __packed; void fsp_set_runtime(FSP_INFO_HEADER *fih, void *hob_list) diff --git a/src/drivers/intel/fsp1_1/include/fsp/gma.h b/src/drivers/intel/fsp1_1/include/fsp/gma.h index b0a2e7ac67..55b09dcb59 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/gma.h +++ b/src/drivers/intel/fsp1_1/include/fsp/gma.h @@ -18,6 +18,7 @@ #define _GMA_H_ #include <types.h> +#include <compiler.h> /* IGD PCI Configuration register */ #define ASLS 0xfc /* OpRegion Base */ @@ -35,7 +36,7 @@ typedef struct { u8 driver_version[16]; u32 mailboxes; u8 reserved[164]; -} __attribute__((packed)) opregion_header_t; +} __packed opregion_header_t; #define IGD_OPREGION_SIGNATURE "IntelGraphicsMem" #define IGD_OPREGION_VERSION 2 @@ -72,7 +73,7 @@ typedef struct { u32 cnot; u32 nrdy; u8 reserved2[60]; -} __attribute__((packed)) opregion_mailbox1_t; +} __packed opregion_mailbox1_t; /* mailbox 2: software sci interface */ typedef struct { @@ -80,7 +81,7 @@ typedef struct { u32 parm; u32 dslp; u8 reserved[244]; -} __attribute__((packed)) opregion_mailbox2_t; +} __packed opregion_mailbox2_t; /* mailbox 3: power conservation */ typedef struct { @@ -99,7 +100,7 @@ typedef struct { u32 ccdv; u32 pcft; u8 reserved[94]; -} __attribute__((packed)) opregion_mailbox3_t; +} __packed opregion_mailbox3_t; #define IGD_BACKLIGHT_BRIGHTNESS 0xff #define IGD_INITIAL_BRIGHTNESS 0x64 @@ -111,7 +112,7 @@ typedef struct { /* mailbox 4: vbt */ typedef struct { u8 gvd1[7168]; -} __attribute__((packed)) opregion_vbt_t; +} __packed opregion_vbt_t; /* IGD OpRegion */ typedef struct { @@ -120,7 +121,7 @@ typedef struct { opregion_mailbox2_t mailbox2; opregion_mailbox3_t mailbox3; opregion_vbt_t vbt; -} __attribute__((packed)) igd_opregion_t; +} __packed igd_opregion_t; /* Intel Video BIOS (Option ROM) */ typedef struct { @@ -129,7 +130,7 @@ typedef struct { u8 reserved[21]; u16 pcir_offset; u16 vbt_offset; -} __attribute__((packed)) optionrom_header_t; +} __packed optionrom_header_t; #define OPROM_SIGNATURE 0xaa55 @@ -146,7 +147,7 @@ typedef struct { u8 codetype; u8 indicator; u16 reserved2; -} __attribute__((packed)) optionrom_pcir_t; +} __packed optionrom_pcir_t; typedef struct { u8 hdr_signature[20]; @@ -170,7 +171,7 @@ typedef struct { u8 coreblock_integratedhw; u8 coreblock_biosbuild[4]; u8 coreblock_biossignon[155]; -} __attribute__((packed)) optionrom_vbt_t; +} __packed optionrom_vbt_t; #define VBT_SIGNATURE 0x54425624 diff --git a/src/drivers/intel/fsp2_0/graphics.c b/src/drivers/intel/fsp2_0/graphics.c index cfd3d16428..3207e1d5b5 100644 --- a/src/drivers/intel/fsp2_0/graphics.c +++ b/src/drivers/intel/fsp2_0/graphics.c @@ -10,6 +10,7 @@ * (at your option) any later version. */ +#include <compiler.h> #include <cbfs.h> #include <console/console.h> #include <fsp/util.h> @@ -37,7 +38,7 @@ struct hob_graphics_info { uint32_t blue_mask; uint32_t reserved_mask; uint32_t pixels_per_scanline; -} __attribute__((packed)); +} __packed; struct pixel { uint8_t pos; diff --git a/src/drivers/intel/fsp2_0/hob_display.c b/src/drivers/intel/fsp2_0/hob_display.c index 7257aec7c5..67e79b48b1 100644 --- a/src/drivers/intel/fsp2_0/hob_display.c +++ b/src/drivers/intel/fsp2_0/hob_display.c @@ -9,13 +9,14 @@ * (at your option) any later version. */ +#include <compiler.h> #include <console/console.h> #include <fsp/util.h> struct hob_type_name { uint16_t type; const char *name; -} __attribute__((packed)); +} __packed; static const struct hob_type_name hob_type_names[] = { { HOB_TYPE_HANDOFF, "HOB_TYPE_HANDOFF" }, diff --git a/src/drivers/intel/fsp2_0/include/fsp/upd.h b/src/drivers/intel/fsp2_0/include/fsp/upd.h index 651170f477..580257bd8e 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/upd.h +++ b/src/drivers/intel/fsp2_0/include/fsp/upd.h @@ -12,6 +12,8 @@ #ifndef _FSP2_0_UPD_H_ #define _FSP2_0_UPD_H_ +#include <compiler.h> + struct FSP_UPD_HEADER { /// /// UPD Region Signature. This signature will be @@ -26,7 +28,7 @@ struct FSP_UPD_HEADER { /// uint8_t Revision; uint8_t Reserved[23]; -} __attribute__((packed)); +} __packed; struct FSPM_ARCH_UPD { /// @@ -59,6 +61,6 @@ struct FSPM_ARCH_UPD { /// uint32_t BootMode; uint8_t Reserved1[8]; -} __attribute__((packed)); +} __packed; #endif /* _FSP2_0_UPD_H_ */ diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index 86e637cec2..402d48b273 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -13,6 +13,7 @@ #ifndef _FSP2_0_UTIL_H_ #define _FSP2_0_UTIL_H_ +#include <compiler.h> #include <boot/coreboot_tables.h> #include <commonlib/region.h> #include <arch/cpu.h> @@ -23,7 +24,7 @@ struct hob_header { uint16_t type; uint16_t length; -} __attribute__((packed)); +} __packed; struct fsp_notify_params { enum fsp_notify_phase phase; @@ -35,7 +36,7 @@ struct hob_resource { uint32_t attribute_type; uint64_t addr; uint64_t length; -} __attribute__((packed)); +} __packed; enum resource_type { EFI_RESOURCE_SYSTEM_MEMORY = 0, diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 424a325958..43888c1bad 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -11,6 +11,7 @@ * (at your option) any later version. */ +#include <compiler.h> #include <antirollback.h> #include <arch/io.h> #include <arch/cpu.h> @@ -281,13 +282,13 @@ static enum cb_err fsp_fill_common_arch_params(FSPM_ARCH_UPD *arch_upd, return CB_SUCCESS; } -__attribute__ ((weak)) +__attribute__((weak)) uint8_t fsp_memory_mainboard_version(void) { return 0; } -__attribute__ ((weak)) +__attribute__((weak)) uint8_t fsp_memory_soc_version(void) { return 0; diff --git a/src/drivers/intel/gma/intel_bios.h b/src/drivers/intel/gma/intel_bios.h index 2e1211b9d1..048985d50b 100644 --- a/src/drivers/intel/gma/intel_bios.h +++ b/src/drivers/intel/gma/intel_bios.h @@ -28,6 +28,8 @@ #ifndef _I830_BIOS_H_ #define _I830_BIOS_H_ +#include <compiler.h> + struct vbt_header { u8 signature[20]; /**< Always starts with 'VBT$' */ u16 version; /**< decimal */ @@ -37,7 +39,7 @@ struct vbt_header { u8 reserved0; u32 bdb_offset; /**< from beginning of VBT */ u32 aim_offset[4]; /**< from beginning of VBT */ -} __attribute__((packed)); +} __packed; struct bdb_header { u8 signature[16]; /**< Always 'BIOS_DATA_BLOCK' */ @@ -63,7 +65,7 @@ struct vbios_data { u8 rsvd4; /* popup memory size */ u8 resize_pci_bios; u8 rsvd5; /* is crt already on ddc2 */ -} __attribute__((packed)); +} __packed; /* * There are several types of BIOS data blocks (BDBs), each block has @@ -140,7 +142,7 @@ struct bdb_general_features { u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */ u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */ u8 rsvd11:3; /* finish byte */ -} __attribute__((packed)); +} __packed; /* pre-915 */ #define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */ @@ -223,7 +225,7 @@ struct old_child_dev_config { u8 dvo2_wiring; u16 extended_type; u8 dvo_function; -} __attribute__((packed)); +} __packed; /* This one contains field offsets that are known to be common for all BDB * versions. Notice that the meaning of the contents contents may still change, @@ -236,7 +238,7 @@ struct common_child_dev_config { u8 not_common2[2]; u8 ddc_pin; u16 edid_ptr; -} __attribute__((packed)); +} __packed; /* This field changes depending on the BDB version, so the most reliable way to * read it is by checking the BDB version and reading the raw pointer. */ @@ -277,7 +279,7 @@ struct bdb_general_definitions { * sizeof(child_device_config); */ union child_device_config devices[0]; -} __attribute__((packed)); +} __packed; struct bdb_lvds_options { u8 panel_type; @@ -291,7 +293,7 @@ struct bdb_lvds_options { u8 lvds_edid:1; u8 rsvd2:1; u8 rsvd4; -} __attribute__((packed)); +} __packed; /* LFP pointer table contains entries to the struct below */ struct bdb_lvds_lfp_data_ptr { @@ -301,12 +303,12 @@ struct bdb_lvds_lfp_data_ptr { u8 dvo_table_size; u16 panel_pnp_id_offset; u8 pnp_table_size; -} __attribute__((packed)); +} __packed; struct bdb_lvds_lfp_data_ptrs { u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */ struct bdb_lvds_lfp_data_ptr ptr[16]; -} __attribute__((packed)); +} __packed; /* LFP data has 3 blocks per entry */ struct lvds_fp_timing { @@ -323,7 +325,7 @@ struct lvds_fp_timing { u32 pfit_reg; u32 pfit_reg_val; u16 terminator; -} __attribute__((packed)); +} __packed; struct lvds_dvo_timing { u16 clock; /**< In 10khz */ @@ -351,7 +353,7 @@ struct lvds_dvo_timing { u8 vsync_positive:1; u8 hsync_positive:1; u8 rsvd2:1; -} __attribute__((packed)); +} __packed; struct lvds_pnp_id { u16 mfg_name; @@ -359,17 +361,17 @@ struct lvds_pnp_id { u32 serial; u8 mfg_week; u8 mfg_year; -} __attribute__((packed)); +} __packed; struct bdb_lvds_lfp_data_entry { struct lvds_fp_timing fp_timing; struct lvds_dvo_timing dvo_timing; struct lvds_pnp_id pnp_id; -} __attribute__((packed)); +} __packed; struct bdb_lvds_lfp_data { struct bdb_lvds_lfp_data_entry data[16]; -} __attribute__((packed)); +} __packed; struct aimdb_header { char signature[16]; @@ -377,12 +379,12 @@ struct aimdb_header { u16 aimdb_version; u16 aimdb_header_size; u16 aimdb_size; -} __attribute__((packed)); +} __packed; struct aimdb_block { u8 aimdb_id; u16 aimdb_size; -} __attribute__((packed)); +} __packed; struct vch_panel_data { u16 fp_timing_offset; @@ -393,12 +395,12 @@ struct vch_panel_data { u8 text_fitting_size; u16 graphics_fitting_offset; u8 graphics_fitting_size; -} __attribute__((packed)); +} __packed; struct vch_bdb_22 { struct aimdb_block aimdb_block; struct vch_panel_data panels[16]; -} __attribute__((packed)); +} __packed; struct bdb_sdvo_lvds_options { u8 panel_backlight; @@ -414,7 +416,7 @@ struct bdb_sdvo_lvds_options { u8 panel_misc_bits_2; u8 panel_misc_bits_3; u8 panel_misc_bits_4; -} __attribute__((packed)); +} __packed; #define BDB_DRIVER_FEATURE_NO_LVDS 0 @@ -460,7 +462,7 @@ struct bdb_driver_features { u8 hdmi_termination; u8 custom_vbt_version; -} __attribute__((packed)); +} __packed; #define EDP_18BPP 0 #define EDP_24BPP 1 @@ -485,14 +487,14 @@ struct edp_power_seq { u16 t9; u16 t10; u16 t11_t12; -} __attribute__ ((packed)); +} __packed; struct edp_link_params { u8 rate:4; u8 lanes:4; u8 preemphasis:4; u8 vswing:4; -} __attribute__ ((packed)); +} __packed; struct bdb_edp { struct edp_power_seq power_seqs[16]; @@ -503,7 +505,7 @@ struct bdb_edp { /* ith bit indicates enabled/disabled for (i+1)th panel */ u16 edp_s3d_feature; u16 edp_t3_optimization; -} __attribute__ ((packed)); +} __packed; /* * Driver<->VBIOS interaction occurs through scratch bits in @@ -728,7 +730,7 @@ struct bdb_mipi { u32 hl_switch_cnt; u32 lp_byte_clk; u32 clk_lane_switch_cnt; -} __attribute__((packed)); +} __packed; #define VBT_SIGNATURE 0x54425624 diff --git a/src/drivers/intel/gma/opregion.h b/src/drivers/intel/gma/opregion.h index 7c7107a8e7..10c1691774 100644 --- a/src/drivers/intel/gma/opregion.h +++ b/src/drivers/intel/gma/opregion.h @@ -19,6 +19,7 @@ #define _COMMON_GMA_H_ #include <types.h> +#include <compiler.h> #include <commonlib/helpers.h> /* IGD PCI Configuration register */ @@ -40,7 +41,7 @@ typedef struct { u32 pcon; /* Offset 96 Platform Capabilities */ u16 dver[16]; /* Offset 100 GOP Version */ u8 reserved[124]; /* Offset 132 Reserved */ -} __attribute__((packed)) opregion_header_t; +} __packed opregion_header_t; #define IGD_OPREGION_SIGNATURE "IntelGraphicsMem" #define IGD_OPREGION_VERSION 2 @@ -121,7 +122,7 @@ typedef struct { u32 cp14; /* Offset 244 Extended Currently present device 6 */ u32 cp15; /* Offset 248 Extended Currently present device 7 */ u8 reserved2[4]; /* Offset 252 Reserved 4 bytes */ -} __attribute__((packed)) opregion_mailbox1_t; +} __packed opregion_mailbox1_t; /* mailbox 2: software sci interface */ typedef struct { @@ -129,7 +130,7 @@ typedef struct { u32 parm; /* Offset 4 Software SCI function number parameters */ u32 dslp; /* Offset 8 Driver sleep timeout */ u8 reserved[244]; /* Offset 12 Reserved */ -} __attribute__((packed)) opregion_mailbox2_t; +} __packed opregion_mailbox2_t; /* mailbox 3: power conservation */ typedef struct { @@ -163,7 +164,7 @@ typedef struct { * Size of Raw VBT data */ u8 reserved[58]; /* Offset 198 Reserved */ -} __attribute__((packed)) opregion_mailbox3_t; +} __packed opregion_mailbox3_t; #define IGD_BACKLIGHT_BRIGHTNESS 0xff #define IGD_INITIAL_BRIGHTNESS 0x64 @@ -175,14 +176,14 @@ typedef struct { /* mailbox 4: vbt */ typedef struct { u8 gvd1[6*KiB]; -} __attribute__((packed)) opregion_vbt_t; +} __packed opregion_vbt_t; /* Mailbox 5: BIOS to Driver Notification Extension */ typedef struct { u32 phed; /* Offset 7168 Panel Header */ u8 bddc[256]; /* Offset 7172 Panel EDID */ u8 reserved[764]; /* Offset 7428 764 bytes */ -} __attribute__((packed)) opregion_mailbox5_t; +} __packed opregion_mailbox5_t; /* IGD OpRegion */ typedef struct { @@ -193,7 +194,7 @@ typedef struct { opregion_vbt_t vbt; opregion_mailbox5_t mailbox5; -} __attribute__((packed)) igd_opregion_t; +} __packed igd_opregion_t; /* Intel Video BIOS (Option ROM) */ typedef struct { @@ -202,7 +203,7 @@ typedef struct { u8 reserved[21]; u16 pcir_offset; u16 vbt_offset; -} __attribute__((packed)) optionrom_header_t; +} __packed optionrom_header_t; #define OPROM_SIGNATURE 0xaa55 @@ -219,7 +220,7 @@ typedef struct { u8 codetype; u8 indicator; u16 reserved2; -} __attribute__((packed)) optionrom_pcir_t; +} __packed optionrom_pcir_t; typedef struct { u8 hdr_signature[20]; @@ -243,7 +244,7 @@ typedef struct { u8 coreblock_integratedhw; u8 coreblock_biosbuild[4]; u8 coreblock_biossignon[155]; -} __attribute__((packed)) optionrom_vbt_t; +} __packed optionrom_vbt_t; void intel_gma_opregion_register(uintptr_t opregion); void intel_gma_restore_opregion(void); diff --git a/src/drivers/intel/mipi_camera/chip.h b/src/drivers/intel/mipi_camera/chip.h index d4b8c02818..a66b8ac212 100644 --- a/src/drivers/intel/mipi_camera/chip.h +++ b/src/drivers/intel/mipi_camera/chip.h @@ -17,6 +17,7 @@ #define __INTEL_MIPI_CAMERA_CHIP_H__ #include <stdint.h> +#include <compiler.h> #define MAX_PWDB_ENTRIES 12 @@ -83,7 +84,7 @@ struct intel_ssdb { uint8_t mipi_data_format; /* MIPI data format */ uint8_t silicon_version; /* Silicon version */ uint8_t customer_id; /* Customer ID */ -} __attribute__((packed)); +} __packed; struct intel_pwdb { char name[32]; /* Name of the resource required by the power @@ -92,7 +93,7 @@ struct intel_pwdb { uint32_t entry_type; /* The type of the current power action */ uint32_t delay_usec; /* The delay time after which power action is performed and this is in unit of usec */ -} __attribute__((packed)); +} __packed; struct drivers_intel_mipi_camera_config { struct intel_ssdb ssdb; diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c index a71f014ced..91c21fecff 100644 --- a/src/drivers/intel/wifi/wifi.c +++ b/src/drivers/intel/wifi/wifi.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <compiler.h> #include <arch/acpi_device.h> #include <arch/acpigen.h> #include <console/console.h> @@ -36,7 +37,7 @@ static int smbios_write_wifi(struct device *dev, int *handle, u16 handle; u8 str; char eos[2]; - } __attribute__((packed)); + } __packed; struct smbios_type_intel_wifi *t = (struct smbios_type_intel_wifi *)*current; diff --git a/src/drivers/siemens/nc_fpga/nc_fpga.h b/src/drivers/siemens/nc_fpga/nc_fpga.h index 0a0b0c6ed0..2cb020012b 100644 --- a/src/drivers/siemens/nc_fpga/nc_fpga.h +++ b/src/drivers/siemens/nc_fpga/nc_fpga.h @@ -16,6 +16,8 @@ #ifndef _SIEMENS_NC_FPGA_H_ #define _SIEMENS_NC_FPGA_H_ +#include <compiler.h> + #define NC_MAGIC_OFFSET 0x020 #define NC_FPGA_MAGIC 0x4E433746 #define NC_CAP1_OFFSET 0x080 @@ -64,6 +66,6 @@ typedef struct { uint16_t hystthreshold; uint16_t res9[4]; uint32_t fanmon; -} __attribute__ ((packed)) fan_ctrl_t; +} __packed fan_ctrl_t; #endif /* _SIEMENS_NC_FPGA_H_ */ diff --git a/src/drivers/usb/ehci.h b/src/drivers/usb/ehci.h index 25c08a0a1b..33b7854df5 100644 --- a/src/drivers/usb/ehci.h +++ b/src/drivers/usb/ehci.h @@ -19,6 +19,8 @@ #ifndef EHCI_H #define EHCI_H +#include <compiler.h> + /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */ /* Section 2.2 Host Controller Capability Registers */ @@ -52,7 +54,7 @@ struct ehci_caps { #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/ #define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */ u8 portroute[8]; /* nibbles for routing - offset 0xC */ -} __attribute__ ((packed)); +} __packed; /* Section 2.3 Host Controller Operational Registers */ @@ -148,7 +150,7 @@ struct ehci_regs { #define PORT_CSC (1<<1) /* connect status change */ #define PORT_CONNECT (1<<0) /* device connected */ #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) -} __attribute__ ((packed)); +} __packed; #define USBMODE 0x68 /* USB Device mode */ #define USBMODE_SDIS (1<<3) /* Stream disable */ @@ -192,7 +194,7 @@ struct ehci_dbg_port { u32 data47; u32 address; #define DBGP_EPADDR(dev, ep) (((dev)<<8)|(ep)) -} __attribute__ ((packed)); +} __packed; #define USB_DEBUG_DEVNUM 127 diff --git a/src/drivers/usb/usb_ch9.h b/src/drivers/usb/usb_ch9.h index 4509287ce4..271b7d1cac 100644 --- a/src/drivers/usb/usb_ch9.h +++ b/src/drivers/usb/usb_ch9.h @@ -17,6 +17,8 @@ #ifndef USB_CH9_H #define USB_CH9_H +#include <compiler.h> + #define USB_DIR_OUT 0 /* to device */ #define USB_DIR_IN 0x80 /* to host */ @@ -111,7 +113,7 @@ struct usb_ctrlrequest { u16 wValue; u16 wIndex; u16 wLength; -} __attribute__ ((packed)); +} __packed; struct usb_debug_descriptor { u8 bLength; diff --git a/src/include/bootstate.h b/src/include/bootstate.h index 4e95ca4f3c..c15cb308d7 100644 --- a/src/include/bootstate.h +++ b/src/include/bootstate.h @@ -183,9 +183,9 @@ struct boot_state_init_entry { }; #if ENV_RAMSTAGE -#define BOOT_STATE_INIT_ATTR __attribute__ ((used, section(".bs_init"))) +#define BOOT_STATE_INIT_ATTR __attribute__((used, section(".bs_init"))) #else -#define BOOT_STATE_INIT_ATTR __attribute__ ((unused)) +#define BOOT_STATE_INIT_ATTR __attribute__((unused)) #endif #define BOOT_STATE_INIT_ENTRY(state_, when_, func_, arg_) \ diff --git a/src/include/compiler.h b/src/include/compiler.h new file mode 100644 index 0000000000..f218725086 --- /dev/null +++ b/src/include/compiler.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __COMPILER_H__ +#define __COMPILER_H__ + +#if defined(__WIN32) || defined(__WIN64) +#define __packed __attribute__((gcc_struct, packed)) +#else +#define __packed __attribute__((packed)) +#endif + +#define __aligned(x) __attribute__((aligned(x))) +#define __always_unused __attribute__((unused)) + +#endif diff --git a/src/include/console/console.h b/src/include/console/console.h index e00482439a..aab0411600 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -40,7 +40,7 @@ void post_log_clear(void); #endif /* this function is weak and can be overridden by a mainboard function. */ void mainboard_post(u8 value); -void __attribute__ ((noreturn)) die(const char *msg); +void __attribute__((noreturn)) die(const char *msg); #define __CONSOLE_ENABLE__ \ ((ENV_BOOTBLOCK && IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) || \ diff --git a/src/include/console/spi.h b/src/include/console/spi.h index dd33b0f375..42566eb768 100644 --- a/src/include/console/spi.h +++ b/src/include/console/spi.h @@ -18,6 +18,7 @@ #include <rules.h> #include <stdint.h> +#include <compiler.h> void spiconsole_init(void); void spiconsole_tx_byte(unsigned char c); @@ -59,12 +60,12 @@ struct em100_msg_header { uint32_t msg_signature; uint8_t msg_type; uint8_t msg_length; -} __attribute__ ((packed)); +} __packed; struct em100_msg { struct em100_msg_header header; char data[MAX_MSG_LENGTH]; -} __attribute__ ((packed)); +} __packed; diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index a78dd2f425..60940f07d1 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -10,7 +10,7 @@ void initialize_cpus(struct bus *cpu_bus); asmlinkage void secondary_cpu_init(unsigned int cpu_index); int cpu_phys_address_size(void); -#define __cpu_driver __attribute__ ((used, __section__(".rodata.cpu_driver"))) +#define __cpu_driver __attribute__((used, __section__(".rodata.cpu_driver"))) #ifndef __SIMPLE_DEVICE__ /** start of compile time generated pci driver array */ extern struct cpu_driver _cpu_drivers[]; diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 15e3ed30da..34e3d05f2c 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -22,6 +22,7 @@ #include <arch/cpu.h> #include <types.h> +#include <compiler.h> #define SMM_DEFAULT_BASE 0x30000 #define SMM_DEFAULT_SIZE 0x10000 @@ -129,7 +130,7 @@ typedef struct { u64 rdx; u64 rcx; u64 rax; -} __attribute__((packed)) amd64_smm_state_save_area_t; +} __packed amd64_smm_state_save_area_t; /* Intel Core 2 (EM64T) SMM State-Save Area @@ -211,7 +212,7 @@ typedef struct { u64 cr3; u64 cr0; -} __attribute__((packed)) em64t_smm_state_save_area_t; +} __packed em64t_smm_state_save_area_t; /* Intel Revision 30100 SMM State-Save Area @@ -298,7 +299,7 @@ typedef struct { u64 cr3; u64 cr0; -} __attribute__((packed)) em64t100_smm_state_save_area_t; +} __packed em64t100_smm_state_save_area_t; /* Intel Revision 30101 SMM State-Save Area * The following processor architectures use this: @@ -397,7 +398,7 @@ typedef struct { u64 cr3; u64 cr0; -} __attribute__((packed)) em64t101_smm_state_save_area_t; +} __packed em64t101_smm_state_save_area_t; /* Legacy x86 SMM State-Save Area @@ -438,7 +439,7 @@ typedef struct { u32 eflags; u32 cr3; u32 cr0; -} __attribute__((packed)) legacy_smm_state_save_area_t; +} __packed legacy_smm_state_save_area_t; typedef enum { AMD64, @@ -514,7 +515,7 @@ struct smm_runtime { * contiguous like the 1:1 mapping it is up to the caller of the stub * loader to adjust this mapping. */ u8 apic_id_to_cpu[CONFIG_MAX_CPUS]; -} __attribute__ ((packed)); +} __packed; struct smm_module_params { void *arg; diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 4f6dfbc590..a04fc10677 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -57,7 +57,7 @@ struct pci_driver { const unsigned short *devices; }; -#define __pci_driver __attribute__ ((used, __section__(".rodata.pci_driver"))) +#define __pci_driver __attribute__((used, __section__(".rodata.pci_driver"))) /** start of compile time generated pci driver array */ extern struct pci_driver _pci_drivers[]; /** end of compile time generated pci driver array */ diff --git a/src/include/elog.h b/src/include/elog.h index c960186c03..e309b58dee 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -16,6 +16,8 @@ #ifndef ELOG_H_ #define ELOG_H_ +#include <compiler.h> + /* SMI command code for GSMI event logging */ #define ELOG_GSMI_APM_CNT 0xEF @@ -151,7 +153,7 @@ struct elog_event_data_wake { u8 source; u32 instance; -} __attribute__ ((packed)); +} __packed; /* Chrome OS related events */ #define ELOG_TYPE_CROS_DEVELOPER_MODE 0xa0 @@ -169,7 +171,7 @@ struct elog_event_data_me_extended { u8 progress_code; u8 current_pmevent; u8 current_state; -} __attribute__ ((packed)); +} __packed; /* Last post code from previous boot */ #define ELOG_TYPE_LAST_POST_CODE 0xa3 @@ -195,7 +197,7 @@ struct elog_event_data_me_extended { struct elog_event_mem_cache_update { u8 slot; u8 status; -} __attribute__ ((packed)); +} __packed; /* CPU Thermal Trip */ #define ELOG_TYPE_THERM_TRIP 0xab diff --git a/src/include/memory_info.h b/src/include/memory_info.h index 02904af285..8569ee493a 100644 --- a/src/include/memory_info.h +++ b/src/include/memory_info.h @@ -17,6 +17,7 @@ #define _MEMORY_INFO_H_ #include <stdint.h> +#include <compiler.h> /* * If this table is filled and put in CBMEM, @@ -37,12 +38,12 @@ struct dimm_info { uint16_t mod_id; uint8_t mod_type; uint8_t bus_width; -} __attribute__((packed)); +} __packed; struct memory_info { uint8_t dimm_cnt; /* Maximum num of dimm is 8 */ struct dimm_info dimm[8]; -} __attribute__((packed)); +} __packed; #endif diff --git a/src/include/reg_script.h b/src/include/reg_script.h index 13af794f1c..116dd9264b 100644 --- a/src/include/reg_script.h +++ b/src/include/reg_script.h @@ -107,7 +107,7 @@ struct reg_script_bus_entry { void (*reg_script_write)(struct reg_script_context *ctx); }; -#define REG_SCRIPT_TABLE_ATTRIBUTE __attribute__ ((used, section(".rsbe_init"))) +#define REG_SCRIPT_TABLE_ATTRIBUTE __attribute__((used, section(".rsbe_init"))) #define REG_SCRIPT_BUS_ENTRY(bus_entry_) \ const struct reg_script_bus_entry *rsbe_ ## bus_entry_ \ diff --git a/src/include/smbios.h b/src/include/smbios.h index 28f8d13939..dec0300eef 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -19,6 +19,7 @@ #define SMBIOS_H #include <types.h> +#include <compiler.h> unsigned long smbios_write_tables(unsigned long start); int smbios_add_string(char *start, const char *str); @@ -230,7 +231,7 @@ struct smbios_entry { u32 struct_table_address; u16 struct_count; u8 smbios_bcd_revision; -} __attribute__((packed)); +} __packed; struct smbios_type0 { u8 type; @@ -249,7 +250,7 @@ struct smbios_type0 { u8 ec_major_release; u8 ec_minor_release; char eos[2]; -} __attribute__((packed)); +} __packed; struct smbios_type1 { u8 type; @@ -264,7 +265,7 @@ struct smbios_type1 { u8 sku; u8 family; char eos[2]; -} __attribute__((packed)); +} __packed; struct smbios_type2 { u8 type; @@ -275,7 +276,7 @@ struct smbios_type2 { u8 version; u8 serial_number; char eos[2]; -} __attribute__((packed)); +} __packed; enum { SMBIOS_ENCLOSURE_OTHER = 0x01, @@ -336,7 +337,7 @@ struct smbios_type3 { u8 element_record_length; u8 sku_number; char eos[2]; -} __attribute__((packed)); +} __packed; struct smbios_type4 { u8 type; @@ -366,7 +367,7 @@ struct smbios_type4 { u16 processor_characteristics; u16 processor_family2; char eos[2]; -} __attribute__((packed)); +} __packed; struct smbios_type11 { u8 type; @@ -374,7 +375,7 @@ struct smbios_type11 { u16 handle; u8 count; char eos[2]; -} __attribute__((packed)); +} __packed; struct smbios_type15 { u8 type; @@ -391,7 +392,7 @@ struct smbios_type15 { u8 log_type_descriptors; u8 log_type_descriptor_length; char eos[2]; -} __attribute__((packed)); +} __packed; enum { SMBIOS_EVENTLOG_ACCESS_METHOD_IO8 = 0, @@ -418,7 +419,7 @@ struct smbios_type16 { u16 number_of_memory_devices; u64 extended_maximum_capacity; char eos[2]; -} __attribute__((packed)); +} __packed; struct smbios_type17 { u8 type; @@ -447,7 +448,7 @@ struct smbios_type17 { u16 maximum_voltage; u16 configured_voltage; char eos[2]; -} __attribute__((packed)); +} __packed; struct smbios_type32 { u8 type; @@ -456,7 +457,7 @@ struct smbios_type32 { u8 reserved[6]; u8 boot_status; u8 eos[2]; -} __attribute__((packed)); +} __packed; struct smbios_type38 { u8 type; @@ -469,7 +470,7 @@ struct smbios_type38 { u64 base_address; u8 base_address_modifier; u8 irq; -} __attribute__((packed)); +} __packed; typedef enum { SMBIOS_DEVICE_TYPE_OTHER = 0x01, @@ -497,14 +498,14 @@ struct smbios_type41 { u8 function_number: 3; u8 device_number: 5; char eos[2]; -} __attribute__((packed)); +} __packed; struct smbios_type127 { u8 type; u8 length; u16 handle; u8 eos[2]; -} __attribute__((packed)); +} __packed; void smbios_fill_dimm_manufacturer_from_id(uint16_t mod_id, struct smbios_type17 *t); diff --git a/src/include/trace.h b/src/include/trace.h index 8745966bc4..05306f0b30 100644 --- a/src/include/trace.h +++ b/src/include/trace.h @@ -28,16 +28,16 @@ #if CONFIG_TRACE && !defined(__SMM__) void __cyg_profile_func_enter(void *, void *) - __attribute__ ((no_instrument_function)); + __attribute__((no_instrument_function)); void __cyg_profile_func_exit(void *, void *) - __attribute__ ((no_instrument_function)); + __attribute__((no_instrument_function)); extern volatile int trace_dis; #define DISABLE_TRACE do { trace_dis = 1; } while (0); #define ENABLE_TRACE do { trace_dis = 0; } while (0); -#define DISABLE_TRACE_ON_FUNCTION __attribute__ ((no_instrument_function)); +#define DISABLE_TRACE_ON_FUNCTION __attribute__((no_instrument_function)); #else /* !CONFIG_TRACE */ diff --git a/src/include/vbe.h b/src/include/vbe.h index 12fac77357..ceceff29fb 100644 --- a/src/include/vbe.h +++ b/src/include/vbe.h @@ -13,6 +13,7 @@ #ifndef VBE_H #define VBE_H +#include <compiler.h> #include <boot/coreboot_tables.h> // these structs are for input from and output to OF typedef struct { @@ -24,7 +25,7 @@ typedef struct { u8 color_depth; // color depth in bits per pixel u32 framebuffer_address; u8 edid_block_zero[128]; -} __attribute__ ((__packed__)) screen_info_t; +} __packed screen_info_t; typedef struct { u8 signature[4]; @@ -32,7 +33,7 @@ typedef struct { u8 monitor_number; u16 max_screen_width; u8 color_depth; -} __attribute__ ((__packed__)) screen_info_input_t; +} __packed screen_info_input_t; // these structs only store a subset of the VBE defined fields // only those needed. @@ -80,7 +81,7 @@ typedef struct { u32 offscreen_mem_offset; u16 offscreen_mem_size; u8 reserved[206]; -} __attribute__ ((__packed__)) vesa_mode_info_t; +} __packed vesa_mode_info_t; typedef struct { u16 video_mode; diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index 34363904b5..d9716700bb 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <compiler.h> #include <console/console.h> #include <console/cbmem_console.h> #include <console/uart.h> @@ -43,7 +44,7 @@ struct cbmem_console { u32 size; u32 cursor; u8 body[0]; -} __attribute__ ((__packed__)); +} __packed; #define MAX_SIZE (1 << 28) /* can't be changed without breaking readers! */ #define CURSOR_MASK (MAX_SIZE - 1) /* bits 31-28 are reserved for flags */ diff --git a/src/lib/gcov-io.h b/src/lib/gcov-io.h index e2c0e0d756..4c0b2e4e42 100644 --- a/src/lib/gcov-io.h +++ b/src/lib/gcov-io.h @@ -181,29 +181,29 @@ permissions described in the GCC Runtime Library Exception, version /* About the target */ #if BITS_PER_UNIT == 8 -typedef unsigned int gcov_unsigned_t __attribute__ ((mode(SI))); -typedef unsigned int gcov_position_t __attribute__ ((mode(SI))); +typedef unsigned int gcov_unsigned_t __attribute__((mode(SI))); +typedef unsigned int gcov_position_t __attribute__((mode(SI))); #if LONG_LONG_TYPE_SIZE > 32 -typedef signed gcov_type __attribute__ ((mode(DI))); +typedef signed gcov_type __attribute__((mode(DI))); #else -typedef signed gcov_type __attribute__ ((mode(SI))); +typedef signed gcov_type __attribute__((mode(SI))); #endif #else #if BITS_PER_UNIT == 16 -typedef unsigned int gcov_unsigned_t __attribute__ ((mode(HI))); -typedef unsigned int gcov_position_t __attribute__ ((mode(HI))); +typedef unsigned int gcov_unsigned_t __attribute__((mode(HI))); +typedef unsigned int gcov_position_t __attribute__((mode(HI))); #if LONG_LONG_TYPE_SIZE > 32 -typedef signed gcov_type __attribute__ ((mode(SI))); +typedef signed gcov_type __attribute__((mode(SI))); #else -typedef signed gcov_type __attribute__ ((mode(HI))); +typedef signed gcov_type __attribute__((mode(HI))); #endif #else -typedef unsigned int gcov_unsigned_t __attribute__ ((mode(QI))); -typedef unsigned int gcov_position_t __attribute__ ((mode(QI))); +typedef unsigned int gcov_unsigned_t __attribute__((mode(QI))); +typedef unsigned int gcov_position_t __attribute__((mode(QI))); #if LONG_LONG_TYPE_SIZE > 32 -typedef signed gcov_type __attribute__ ((mode(HI))); +typedef signed gcov_type __attribute__((mode(HI))); #else -typedef signed gcov_type __attribute__ ((mode(QI))); +typedef signed gcov_type __attribute__((mode(QI))); #endif #endif #endif @@ -270,7 +270,7 @@ typedef HOST_WIDEST_INT gcov_type; #pragma GCC poison gcov_read_string gcov_sync gcov_time gcov_magic #ifdef HAVE_GAS_HIDDEN -#define ATTRIBUTE_HIDDEN __attribute__ ((__visibility__("hidden"))) +#define ATTRIBUTE_HIDDEN __attribute__((__visibility__("hidden"))) #else #define ATTRIBUTE_HIDDEN #endif diff --git a/src/lib/imd.c b/src/lib/imd.c index 8f65fa8285..d17cc815ce 100644 --- a/src/lib/imd.c +++ b/src/lib/imd.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <compiler.h> #include <assert.h> #include <cbmem.h> #include <console/console.h> @@ -32,7 +33,7 @@ struct imd_root_pointer { uint32_t magic; /* Relative to upper limit/offset. */ int32_t root_offset; -} __attribute__((packed)); +} __packed; struct imd_entry { uint32_t magic; @@ -40,7 +41,7 @@ struct imd_entry { int32_t start_offset; uint32_t size; uint32_t id; -} __attribute__((packed)); +} __packed; struct imd_root { uint32_t max_entries; @@ -50,7 +51,7 @@ struct imd_root { /* Used for fixing the size of an imd. Relative to the root. */ int32_t max_offset; struct imd_entry entries[0]; -} __attribute__((packed)); +} __packed; #define IMD_FLAG_LOCKED 1 diff --git a/src/lib/libgcov.c b/src/lib/libgcov.c index ca5021f834..70a4073253 100644 --- a/src/lib/libgcov.c +++ b/src/lib/libgcov.c @@ -73,23 +73,23 @@ typedef s32 pid_t; /* If libc and its header files are not available, provide dummy functions. */ #ifdef L_gcov -void __gcov_init(struct gcov_info *p __attribute__ ((unused))) {} +void __gcov_init(struct gcov_info *p __attribute__((unused))) {} void __gcov_flush(void) {} #endif #ifdef L_gcov_merge_add -void __gcov_merge_add(gcov_type *counters __attribute__ ((unused)), - unsigned int n_counters __attribute__ ((unused))) {} +void __gcov_merge_add(gcov_type *counters __attribute__((unused)), + unsigned int n_counters __attribute__((unused))) {} #endif #ifdef L_gcov_merge_single -void __gcov_merge_single(gcov_type *counters __attribute__ ((unused)), - unsigned int n_counters __attribute__ ((unused))) {} +void __gcov_merge_single(gcov_type *counters __attribute__((unused)), + unsigned int n_counters __attribute__((unused))) {} #endif #ifdef L_gcov_merge_delta -void __gcov_merge_delta(gcov_type *counters __attribute__ ((unused)), - unsigned int n_counters __attribute__ ((unused))) {} +void __gcov_merge_delta(gcov_type *counters __attribute__((unused)), + unsigned int n_counters __attribute__((unused))) {} #endif #else @@ -102,8 +102,8 @@ void __gcov_merge_delta(gcov_type *counters __attribute__ ((unused)), #include <sys/stat.h> #endif #else -void __gcov_merge_add(gcov_type *counters __attribute__ ((unused)), - unsigned int n_counters __attribute__ ((unused))) {} +void __gcov_merge_add(gcov_type *counters __attribute__((unused)), + unsigned int n_counters __attribute__((unused))) {} #endif /* __COREBOOT__ */ #ifdef L_gcov diff --git a/src/lib/prog_ops.c b/src/lib/prog_ops.c index bc889fceae..44a32d19bf 100644 --- a/src/lib/prog_ops.c +++ b/src/lib/prog_ops.c @@ -23,13 +23,13 @@ void prog_segment_loaded(uintptr_t start, size_t size, int flags) arch_segment_loaded(start, size, flags); } -void __attribute__ ((weak)) platform_segment_loaded(uintptr_t start, +void __attribute__((weak)) platform_segment_loaded(uintptr_t start, size_t size, int flags) { /* do nothing */ } -void __attribute__ ((weak)) arch_segment_loaded(uintptr_t start, size_t size, +void __attribute__((weak)) arch_segment_loaded(uintptr_t start, size_t size, int flags) { /* do nothing */ @@ -41,7 +41,7 @@ void prog_run(struct prog *prog) arch_prog_run(prog); } -void __attribute__ ((weak)) platform_prog_run(struct prog *prog) +void __attribute__((weak)) platform_prog_run(struct prog *prog) { /* do nothing */ } diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 5f84cf4ac8..816f28fd85 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -16,6 +16,7 @@ #include <assert.h> #include <stddef.h> #include <stdint.h> +#include <compiler.h> #include <console/console.h> #include <cbmem.h> #include <symbols.h> @@ -30,7 +31,7 @@ /* When changing this number, adjust TIMESTAMP() size ASSERT() in memlayout.h */ #define MAX_BSS_TIMESTAMP_CACHE 16 -struct __attribute__((__packed__)) timestamp_cache { +struct __packed timestamp_cache { uint32_t cache_state; struct timestamp_table table; /* The struct timestamp_table has a 0 length array as its last field. diff --git a/src/lib/tpm2_tlcl_structures.h b/src/lib/tpm2_tlcl_structures.h index 4ea20783e5..2a6615df42 100644 --- a/src/lib/tpm2_tlcl_structures.h +++ b/src/lib/tpm2_tlcl_structures.h @@ -12,6 +12,7 @@ * constants and structures needed for functions used in coreboot. */ #include <stdint.h> +#include <compiler.h> #include <tpm_lite/tlcl.h> #include <types.h> @@ -56,7 +57,7 @@ struct tpm_header { uint16_t tpm_tag; uint32_t tpm_size; TPM_CC tpm_code; -} __attribute__((packed)); +} __packed; /* TPM command codes. */ #define TPM2_Hierarchy_Control ((TPM_CC)0x00000121) @@ -318,7 +319,7 @@ struct tpm2_session_header { union { struct tpm2_session_attrs session_attr_bits; uint8_t session_attrs; - } __attribute__((packed)); + } __packed; uint16_t auth_size; uint8_t *auth; }; diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index 903bd83a4e..4db148cdba 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -11,6 +11,7 @@ * GNU General Public License for more details. */ +#include <compiler.h> #include <string.h> #include <swab.h> #include <smbios.h> @@ -186,7 +187,7 @@ struct BiosLinkerLoaderEntry { /* padding */ char pad[124]; }; -} __attribute__((packed)); +} __packed; typedef struct BiosLinkerLoaderEntry BiosLinkerLoaderEntry; enum { diff --git a/src/mainboard/siemens/mc_apl1/ptn3460.h b/src/mainboard/siemens/mc_apl1/ptn3460.h index db6310bcd2..90b509c328 100644 --- a/src/mainboard/siemens/mc_apl1/ptn3460.h +++ b/src/mainboard/siemens/mc_apl1/ptn3460.h @@ -17,6 +17,7 @@ #define PTN3460_H_ #include <stdint.h> +#include <compiler.h> #define PTN_SLAVE_ADR 0x20 #define PTN_I2C_CONTROLLER 0 @@ -74,7 +75,7 @@ struct ptn_3460_config { uint8_t t4_timing; /* Panel T5 delay. */ uint8_t t5_delay; -} __attribute__((packed)); +} __packed; struct ptn_3460_flash { /* Flash command (erase or erase and flash). */ @@ -83,7 +84,7 @@ struct ptn_3460_flash { uint16_t magic; /* Trigger for starting flash operation. */ uint8_t trigger; -} __attribute__((packed)); +} __packed; int ptn3460_init(const char *hwi_block); int ptn3460_write_edid(uint8_t edid_num, const uint8_t data[PTN_EDID_LEN]); diff --git a/src/mainboard/siemens/mc_tcu3/ptn3460.h b/src/mainboard/siemens/mc_tcu3/ptn3460.h index 533607c194..e662f6101e 100644 --- a/src/mainboard/siemens/mc_tcu3/ptn3460.h +++ b/src/mainboard/siemens/mc_tcu3/ptn3460.h @@ -16,6 +16,7 @@ #ifndef PTN3460_H_ #define PTN3460_H_ +#include <compiler.h> #include <delay.h> #include "lcd_panel.h" @@ -56,13 +57,13 @@ struct ptn_3460_config{ u8 t2_delay; /* Panel T2 delay */ u8 t4_timing; /* Panel T4 timing value */ u8 t5_delay; /* Panel T5 delay */ -}__attribute__((packed)); +} __packed; struct ptn_3460_flash{ u8 cmd; /* Flash command (erase or erase and flash) */ u16 magic; /* Magic number needed by the flash algorithm */ u8 trigger; /* Trigger for starting flash operation */ -}__attribute__((packed)); +} __packed; int ptn3460_init(char *hwi_block); diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c index 30f963e729..0787d7ae7f 100644 --- a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c +++ b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include <compiler.h> #include <console/console.h> #include <string.h> #include <arch/acpi.h> @@ -39,7 +40,7 @@ typedef struct { u32 pcba; u8 mpen; u8 reserv[247]; -} __attribute__((packed)) global_vars_t; +} __packed global_vars_t; static void acpi_write_gvars(global_vars_t *gvars) { diff --git a/src/mainboard/via/epia-m700/wakeup.c b/src/mainboard/via/epia-m700/wakeup.c index ec4d07a469..f4c2d852c6 100644 --- a/src/mainboard/via/epia-m700/wakeup.c +++ b/src/mainboard/via/epia-m700/wakeup.c @@ -26,6 +26,7 @@ * acpi_jump_wake(). */ +#include <compiler.h> #include <stdint.h> #include <string.h> #include <arch/io.h> @@ -52,9 +53,9 @@ static unsigned long long real_mode_gdt_entries[3] = { struct Xgt_desc_struct { unsigned short size; - unsigned long address __attribute__ ((packed)); + unsigned long address __packed; unsigned short pad; -} __attribute__ ((packed)); +} __packed; static struct Xgt_desc_struct real_mode_gdt = { sizeof(real_mode_gdt_entries) - 1, diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 611291acbd..e9f714a62e 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -18,6 +18,7 @@ #define AMDFAM10_H #include <inttypes.h> +#include <compiler.h> #include <arch/io.h> #include <device/device.h> #include "early_ht.h" @@ -934,14 +935,14 @@ struct link_pair_t { u8 nodeid; u8 linkn; u8 rsv; -} __attribute__((packed)); +} __packed; struct nodes_info_t { u32 nodes_in_group; // could be 2, 3, 4, 5, 6, 7, 8 u32 groups_in_plane; // could be 1, 2, 3, 4, 5 u32 planes; // could be 1, 2 u32 up_planes; // down planes will be [up_planes, planes) -} __attribute__((packed)); +} __packed; struct ht_link_config { uint32_t ht_speed_limit; // Speed in MHz; 0 for autodetect (default) @@ -977,7 +978,7 @@ struct sys_info { struct MCTStatStruc MCTstat; struct DCTStatStruc DCTstatA[NODE_NUMS]; -} __attribute__((packed)); +} __packed; /* diff --git a/src/northbridge/amd/amdk8/f.h b/src/northbridge/amd/amdk8/f.h index f3f9c42614..9f09620c95 100644 --- a/src/northbridge/amd/amdk8/f.h +++ b/src/northbridge/amd/amdk8/f.h @@ -1,6 +1,8 @@ #ifndef AMDK8_F_H #define AMDK8_F_H +#include <compiler.h> + /* Definitions of various K8 registers */ /* Function 0 */ #define HT_TRANSACTION_CONTROL 0x68 @@ -465,7 +467,7 @@ struct dimm_size { uint8_t col; uint8_t bank; //1, 2, 3 mean 2, 4, 8 uint8_t rank; -} __attribute__((packed)); +} __packed; struct mem_info { // pernode uint32_t dimm_mask; @@ -483,7 +485,7 @@ struct mem_info { // pernode uint8_t is_64MuxMode; uint8_t memclk_set; // we need to use this to retrieve the mem param uint8_t rsv[2]; -} __attribute__((packed)); +} __packed; struct link_pair_st { pci_devfn_t udev; @@ -493,7 +495,7 @@ struct link_pair_st { uint32_t pos; uint32_t offs; -} __attribute__((packed)); +} __packed; struct sys_info { uint8_t ctrl_present[NODE_NUMS]; @@ -516,7 +518,7 @@ struct sys_info { uint32_t sbdn; uint32_t sblk; uint32_t sbbusn; -} __attribute__((packed)); +} __packed; #ifdef __PRE_RAM__ #include <arch/early_variables.h> diff --git a/src/northbridge/amd/amdk8/pre_f.h b/src/northbridge/amd/amdk8/pre_f.h index abc51b111f..5b1478bf3c 100644 --- a/src/northbridge/amd/amdk8/pre_f.h +++ b/src/northbridge/amd/amdk8/pre_f.h @@ -1,6 +1,8 @@ #ifndef AMDK8_PRE_F_H #define AMDK8_PRE_F_H +#include <compiler.h> + /* Definitions of various K8 registers */ /* Function 0 */ #define HT_TRANSACTION_CONTROL 0x68 @@ -247,7 +249,7 @@ struct link_pair_st { uint32_t pos; uint32_t offs; -} __attribute__((packed)); +} __packed; struct sys_info { uint8_t ctrl_present[NODE_NUMS]; @@ -260,7 +262,7 @@ struct sys_info { uint32_t sbdn; uint32_t sblk; uint32_t sbbusn; -} __attribute__((packed)); +} __packed; #ifdef __PRE_RAM__ #include <arch/early_variables.h> diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h index d13143d979..6a69cfae8c 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.h +++ b/src/northbridge/amd/amdmct/mct/mct_d.h @@ -23,6 +23,7 @@ #define DQS_TRAIN_DEBUG 0 #include <inttypes.h> +#include <compiler.h> #include "mct_d_gcc.h" #include <console/console.h> #include <northbridge/amd/amdfam10/debug.h> @@ -275,7 +276,7 @@ struct MCTStatStruc { of sub 4GB dram hole for HW remapping.*/ u32 Sub4GCacheTop; /* If not zero, the 32-bit top of cacheable memory.*/ u32 SysLimit; /* LIMIT[39:8] (system address)*/ -} __attribute__((packed)); +} __packed; /*============================================================================= Global MCT Configuration Status Word (GStatus) @@ -321,7 +322,7 @@ struct DCTPersistentStatStruc { /* CHB DIMM 0 - 4 Check Byte Receiver Enable Delay*/ u16 HostBiosSrvc1; /* Word sized general purpose field for use by host BIOS. Scratch space.*/ u32 HostBiosSrvc2; /* Dword sized general purpose field for use by host BIOS. Scratch space.*/ -} __attribute__((packed)); +} __packed; struct DCTStatStruc { /* A per Node structure*/ @@ -549,7 +550,7 @@ struct DCTStatStruc { /* A per Node structure*/ /* NOTE: This must remain the last entry in this structure */ struct DCTPersistentStatStruc persistentData; -} __attribute__((packed)); +} __packed; /*=============================================================================== Local Error Status Codes (DCTStatStruc.ErrCode) @@ -717,7 +718,7 @@ struct amdmct_memory_info { struct DCTStatStruc dct_stat[MAX_NODES_SUPPORTED]; uint16_t ecc_enabled; uint16_t ecc_scrub_rate; -} __attribute__((packed)); +} __packed; u32 Get_NB32(u32 dev, u32 reg); void Set_NB32(u32 dev, u32 reg, u32 val); diff --git a/src/northbridge/intel/common/mrc_cache.h b/src/northbridge/intel/common/mrc_cache.h index 1fb6667669..6f0dd6ef74 100644 --- a/src/northbridge/intel/common/mrc_cache.h +++ b/src/northbridge/intel/common/mrc_cache.h @@ -1,6 +1,8 @@ #ifndef NORTHBRIDGE_INTEL_COMMON_MRC_CACHE_H #define NORTHBRIDGE_INTEL_COMMON_MRC_CACHE_H +#include <compiler.h> + #define MRC_DATA_ALIGN 0x1000 #define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) @@ -10,7 +12,7 @@ struct mrc_data_container { u32 mrc_checksum; // IP style checksum u32 reserved; // For header alignment u8 mrc_data[0]; // Variable size, platform/run time dependent. -} __attribute__ ((packed)); +} __packed; struct mrc_data_container *find_current_mrc_cache(void); struct mrc_data_container *store_current_mrc_cache(void *data, unsigned length); diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 00616afb49..2d03a68da1 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -186,13 +186,14 @@ #define DMIDRCCFG 0xeb4 /* 32bit */ #ifndef __ASSEMBLER__ +#include <compiler.h> static inline void barrier(void) { asm("" ::: "memory"); } struct ied_header { char signature[10]; u32 size; u8 reserved[34]; -} __attribute__ ((packed)); +} __packed; #define PCI_DEVICE_ID_HSW_MOBILE 0x0c04 #define PCI_DEVICE_ID_HSW_ULT 0x0a04 diff --git a/src/northbridge/intel/haswell/pei_data.h b/src/northbridge/intel/haswell/pei_data.h index f92c0a68e0..f4023e0a6b 100644 --- a/src/northbridge/intel/haswell/pei_data.h +++ b/src/northbridge/intel/haswell/pei_data.h @@ -30,6 +30,8 @@ #ifndef PEI_DATA_H #define PEI_DATA_H +#include <compiler.h> + typedef void (*tx_byte_func)(unsigned char byte); #define PEI_VERSION 15 @@ -56,12 +58,12 @@ struct usb2_port_setting { uint8_t enable; uint8_t over_current_pin; uint8_t location; -} __attribute__((packed)); +} __packed; struct usb3_port_setting { uint8_t enable; uint8_t over_current_pin; -} __attribute__((packed)); +} __packed; struct pei_data { @@ -110,6 +112,6 @@ struct pei_data struct usb3_port_setting usb3_ports[MAX_USB3_PORTS]; uint8_t spd_data[4][256]; tx_byte_func tx_byte; -} __attribute__((packed)); +} __packed; #endif diff --git a/src/northbridge/intel/i82830/smihandler.c b/src/northbridge/intel/i82830/smihandler.c index 51841e5969..569e62ec7b 100644 --- a/src/northbridge/intel/i82830/smihandler.c +++ b/src/northbridge/intel/i82830/smihandler.c @@ -15,6 +15,7 @@ */ #include <types.h> +#include <compiler.h> #include <string.h> #include <arch/io.h> #include <console/console.h> @@ -51,7 +52,7 @@ typedef struct { u32 function; u32 retsts; u32 rfu; -} __attribute__((packed)) banner_id_t; +} __packed banner_id_t; #define MSH_OK 0x0000 #define MSH_OK_RESTART 0x0001 @@ -111,7 +112,7 @@ typedef struct { u16 versionmajor; u16 versionminor; u32 smicombuffersize; -} __attribute__((packed)) version_t; +} __packed version_t; typedef struct { u16 header_id; @@ -122,14 +123,14 @@ typedef struct { u32 type; u32 header_ext; u8 name[0]; -} __attribute__((packed)) mbi_header_t; +} __packed mbi_header_t; typedef struct { banner_id_t banner; u64 handle; u32 objnum; mbi_header_t header; -} __attribute__((packed)) obj_header_t; +} __packed obj_header_t; typedef struct { banner_id_t banner; @@ -139,7 +140,7 @@ typedef struct { u32 numbytes; u32 buflen; u32 buffer; -} __attribute__((packed)) get_object_t; +} __packed get_object_t; static void mbi_call(u8 subf, banner_id_t *banner_id) { diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index bc4491fe2f..4c97d05b7d 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -16,6 +16,8 @@ #ifndef RAMINIT_H #define RAMINIT_H +#include <compiler.h> + #define DIMM_SOCKETS 2 #define DIMM_TCO_BASE 0x30 @@ -61,7 +63,7 @@ struct sys_info { u8 banksize[2 * 2 * DIMM_SOCKETS]; const u8 *spd_addresses; -} __attribute__ ((packed)); +} __packed; void receive_enable_adjust(struct sys_info *sysinfo); void sdram_initialize(int boot_path, const u8 *sdram_addresses); diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 122b8ac7cf..b7b445ec86 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -22,6 +22,7 @@ #if REAL #include <stdlib.h> +#include <compiler.h> #include <console/console.h> #include <string.h> #include <arch/io.h> @@ -1906,7 +1907,7 @@ static void send_heci_uma_message(struct raminfo *info) u8 result; u8 field2; u8 unk3[0x48 - 4 - 1]; - } __attribute__ ((packed)) reply; + } __packed reply; struct uma_message { u8 group_id; u8 cmd; @@ -1916,7 +1917,7 @@ static void send_heci_uma_message(struct raminfo *info) u64 heci_uma_addr; u32 memory_reserved_for_heci_mb; u16 c3; - } __attribute__ ((packed)) msg = { + } __packed msg = { 0, MKHI_SET_UMA, 0, 0, 0x82, info->heci_uma_addr, info->memory_reserved_for_heci_mb, 0}; diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h index 136d31046e..41fc33fd9a 100644 --- a/src/northbridge/intel/sandybridge/pei_data.h +++ b/src/northbridge/intel/sandybridge/pei_data.h @@ -30,6 +30,8 @@ #ifndef PEI_DATA_H #define PEI_DATA_H +#include <compiler.h> + typedef struct { uint16_t mode; // 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto uint16_t hs_port_switch_mask; // 4 bit mask, 1: switchable, 0: not switchable @@ -129,6 +131,6 @@ struct pei_data * 2 Always enable double rate */ int ddr_refresh_rate_config; -} __attribute__((packed)); +} __packed; #endif diff --git a/src/northbridge/intel/sandybridge/raminit.h b/src/northbridge/intel/sandybridge/raminit.h index 4e684ec409..66a94f48d8 100644 --- a/src/northbridge/intel/sandybridge/raminit.h +++ b/src/northbridge/intel/sandybridge/raminit.h @@ -16,6 +16,7 @@ #ifndef RAMINIT_H #define RAMINIT_H +#include <compiler.h> #include "pei_data.h" struct sys_info { @@ -23,7 +24,7 @@ struct sys_info { #define BOOT_PATH_NORMAL 0 #define BOOT_PATH_RESET 1 #define BOOT_PATH_RESUME 2 -} __attribute__ ((packed)); +} __packed; void sdram_initialize(struct pei_data *pei_data); void save_mrc_data(struct pei_data *pei_data); diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 3f7d1c64ba..7145841ac2 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <compiler.h> #include <console/console.h> #include <console/usb.h> #include <bootmode.h> @@ -183,7 +184,7 @@ static void report_memory_config(void) void sdram_initialize(struct pei_data *pei_data) { struct sys_info sysinfo; - int (*entry) (struct pei_data *pei_data) __attribute__ ((regparm(1))); + int (*entry) (struct pei_data *pei_data) __attribute__((regparm(1))); report_platform_info(); diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index 2d40aed04d..c70c0b1032 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -17,6 +17,7 @@ #define AMD_PSP_H #include <stdint.h> +#include <compiler.h> #include <Porting.h> #include <Proc/Psp/PspBaseLib/PspBaseLib.h> @@ -48,7 +49,7 @@ struct psp_mbox { u32 mbox_command; u32 mbox_status; u64 cmd_response; /* definition conflicts w/BKDG but matches agesa */ -} __attribute__ ((packed)); +} __packed; /* command/response format, BIOS builds this in memory * mbox_buffer_header: generic header @@ -59,7 +60,7 @@ struct psp_mbox { struct mbox_buffer_header { u32 size; /* total size of buffer */ u32 status; /* command status, filled by PSP if applicable */ -} __attribute__ ((packed)); +} __packed; /* command-specific buffer definitions: see NDA document #54267 * todo: create new definitions here for additional c2p_mbox_command commands @@ -67,7 +68,7 @@ struct mbox_buffer_header { struct mbox_default_buffer { /* command-response buffer unused by command */ struct mbox_buffer_header header; -} __attribute__ ((packed,aligned(32))); +} __attribute__((packed,aligned(32))); /* send_psp_command() error codes */ #define PSPSTS_SUCCESS 0 diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c index a571a654d6..515d32b99c 100644 --- a/src/soc/intel/apollolake/cse.c +++ b/src/soc/intel/apollolake/cse.c @@ -21,6 +21,7 @@ #include <intelblocks/cse.h> #include <soc/pci_devs.h> #include <stdint.h> +#include <compiler.h> #define PCI_ME_HFSTS1 0x40 #define PCI_ME_HFSTS2 0x48 @@ -69,7 +70,7 @@ static int read_cse_file(const char *path, void *buff, size_t *size, uint32_t is_response: 1; uint32_t reserved: 8; uint32_t result: 8; - } __attribute__ ((packed)) fields; + } __packed fields; }; struct mca_command { @@ -78,13 +79,13 @@ static int read_cse_file(const char *path, void *buff, size_t *size, uint32_t offset; uint32_t data_size; uint8_t flags; - } __attribute__ ((packed)) msg; + } __packed msg; struct mca_response { union mkhi_header mkhi_hdr; uint32_t data_size; uint8_t buffer[128]; - } __attribute__ ((packed)) rmsg; + } __packed rmsg; if (sizeof(rmsg.buffer) < *size) { printk(BIOS_ERR, "internal buffer is too small\n"); diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index e0b223fa48..56085b25a6 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -24,6 +24,7 @@ #ifndef _SOC_APOLLOLAKE_NVS_H_ #define _SOC_APOLLOLAKE_NVS_H_ +#include <compiler.h> #include <vendorcode/google/chromeos/gnvs.h> typedef struct global_nvs_t { @@ -45,6 +46,6 @@ typedef struct global_nvs_t { /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; -} __attribute__((packed)) global_nvs_t; +} __packed global_nvs_t; #endif /* _SOC_APOLLOLAKE_NVS_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 6c189198ab..b6b6e7b5e2 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -19,6 +19,7 @@ #define _SOC_APOLLOLAKE_PM_H_ #include <stdint.h> +#include <compiler.h> #include <arch/acpi.h> /* ACPI_BASE_ADDRESS */ @@ -201,7 +202,7 @@ struct chipset_power_state { uint32_t gen_pmcon2; uint32_t gen_pmcon3; uint32_t prev_sleep_state; -} __attribute__((packed)); +} __packed; int fill_power_state(struct chipset_power_state *ps); int chipset_prev_sleep_state(struct chipset_power_state *ps); diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 79b3cfd7f9..24e00df3fd 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -48,6 +48,7 @@ #include <timestamp.h> #include <timer.h> #include <delay.h> +#include <compiler.h> #include "chip.h" static struct chipset_power_state power_state CAR_GLOBAL; @@ -372,13 +373,13 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) car_set_var(fsp_version, version); } -__attribute__ ((weak)) +__attribute__((weak)) void mainboard_memory_init_params(FSPM_UPD *mupd) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } -__attribute__ ((weak)) +__attribute__((weak)) void mainboard_save_dimm_info(void) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); diff --git a/src/soc/intel/baytrail/include/soc/device_nvs.h b/src/soc/intel/baytrail/include/soc/device_nvs.h index 5ac95e45b2..b4fe65e7d9 100644 --- a/src/soc/intel/baytrail/include/soc/device_nvs.h +++ b/src/soc/intel/baytrail/include/soc/device_nvs.h @@ -17,6 +17,7 @@ #define _BAYTRAIL_DEVICE_NVS_H_ #include <stdint.h> +#include <compiler.h> /* Offset in Global NVS where this structure lives */ #define DEVICE_NVS_OFFSET 0x1000 @@ -59,6 +60,6 @@ typedef struct { /* Extra */ u32 lpe_fw; /* LPE Firmware */ u8 rsvd1[3930]; /* Add padding so sizeof(device_nvs_t) == 0x1000 */ -} __attribute__((packed)) device_nvs_t; +} __packed device_nvs_t; #endif diff --git a/src/soc/intel/baytrail/include/soc/efi_wrapper.h b/src/soc/intel/baytrail/include/soc/efi_wrapper.h index 3304d03451..3425aae823 100644 --- a/src/soc/intel/baytrail/include/soc/efi_wrapper.h +++ b/src/soc/intel/baytrail/include/soc/efi_wrapper.h @@ -29,6 +29,8 @@ #ifndef __EFI_WRAPPER_H__ #define __EFI_WRAPPER_H__ +#include <compiler.h> + #define EFI_WRAPPER_VER 2 /* Provide generic x86 calling conventions. */ @@ -46,7 +48,7 @@ struct efi_wrapper_params { void ABI_X86 (*console_out)(unsigned char byte); unsigned int tsc_ticks_per_microsecond; -} __attribute__((packed)); +} __packed; typedef int ABI_X86 (*efi_wrapper_entry_t)(struct efi_wrapper_params *); #endif diff --git a/src/soc/intel/baytrail/include/soc/gpio.h b/src/soc/intel/baytrail/include/soc/gpio.h index 9c6b7fd025..0e0395a536 100644 --- a/src/soc/intel/baytrail/include/soc/gpio.h +++ b/src/soc/intel/baytrail/include/soc/gpio.h @@ -17,6 +17,7 @@ #define _BAYTRAIL_GPIO_H_ #include <stdint.h> +#include <compiler.h> #include <arch/io.h> #include <soc/iomap.h> @@ -352,7 +353,7 @@ struct soc_gpio_map { u32 smi : 1; u32 is_gpio : 1; u32 sci : 1; -} __attribute__ ((packed)); +} __packed; struct soc_gpio_config { const struct soc_gpio_map *ncore; diff --git a/src/soc/intel/baytrail/include/soc/mrc_wrapper.h b/src/soc/intel/baytrail/include/soc/mrc_wrapper.h index 355dce0706..d3547c2fb2 100644 --- a/src/soc/intel/baytrail/include/soc/mrc_wrapper.h +++ b/src/soc/intel/baytrail/include/soc/mrc_wrapper.h @@ -28,6 +28,8 @@ #ifndef _MRC_WRAPPER_H_ #define _MRC_WRAPPER_H_ +#include <compiler.h> + #define MRC_PARAMS_VER 5 #define NUM_CHANNELS 2 @@ -76,7 +78,7 @@ struct mrc_mainboard_params { int dram_odt_value; int spd_addrs[NUM_CHANNELS]; void *dram_data[NUM_CHANNELS]; /* SPD or Timing specific data. */ -} __attribute__((packed)); +} __packed; struct mrc_params { /* Mainboard Inputs */ @@ -99,7 +101,7 @@ struct mrc_params { void *txe_base_address; int data_to_save_size; void *data_to_save; -} __attribute__((packed)); +} __packed; /* Call into wrapper. */ typedef int ABI_X86 (*mrc_wrapper_entry_t)(struct mrc_params *); diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h index cb4e9bf18f..8e6819d3b2 100644 --- a/src/soc/intel/baytrail/include/soc/nvs.h +++ b/src/soc/intel/baytrail/include/soc/nvs.h @@ -17,6 +17,7 @@ #ifndef _BAYTRAIL_NVS_H_ #define _BAYTRAIL_NVS_H_ +#include <compiler.h> #include <vendorcode/google/chromeos/gnvs.h> #include <soc/device_nvs.h> @@ -64,7 +65,7 @@ typedef struct { /* Baytrail LPSS (0x1000) */ device_nvs_t dev; -} __attribute__((packed)) global_nvs_t; +} __packed global_nvs_t; void acpi_create_gnvs(global_nvs_t *gnvs); #ifdef __SMM__ diff --git a/src/soc/intel/baytrail/include/soc/pmc.h b/src/soc/intel/baytrail/include/soc/pmc.h index c8d6a67a81..1059d3cd6c 100644 --- a/src/soc/intel/baytrail/include/soc/pmc.h +++ b/src/soc/intel/baytrail/include/soc/pmc.h @@ -16,6 +16,7 @@ #ifndef _BAYTRAIL_PMC_H_ #define _BAYTRAIL_PMC_H_ +#include <compiler.h> #include <arch/acpi.h> #define IOCOM1 0x3f8 @@ -262,7 +263,7 @@ struct chipset_power_state { uint32_t prsts; uint32_t gen_pmcon1; uint32_t gen_pmcon2; -} __attribute__((packed)); +} __packed; /* Power Management Utility Functions. */ uint16_t get_pmbase(void); diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index 6061116c52..340c00c27c 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -14,6 +14,7 @@ /* This file is derived from the flashrom project. */ #include <stdint.h> +#include <compiler.h> #include <stdlib.h> #include <string.h> #include <bootstate.h> @@ -93,7 +94,7 @@ typedef struct ich9_spi_regs { uint32_t srdl; uint32_t srdc; uint32_t srd; -} __attribute__((packed)) ich9_spi_regs; +} __packed ich9_spi_regs; typedef struct ich_spi_controller { int locked; diff --git a/src/soc/intel/braswell/include/soc/device_nvs.h b/src/soc/intel/braswell/include/soc/device_nvs.h index 6318918b71..268655e7cb 100644 --- a/src/soc/intel/braswell/include/soc/device_nvs.h +++ b/src/soc/intel/braswell/include/soc/device_nvs.h @@ -18,6 +18,7 @@ #define _SOC_DEVICE_NVS_H_ #include <stdint.h> +#include <compiler.h> /* Offset in Global NVS where this structure lives */ #define DEVICE_NVS_OFFSET 0x1000 @@ -59,6 +60,6 @@ typedef struct { /* Extra */ u32 lpe_fw; /* LPE Firmware */ -} __attribute__((packed)) device_nvs_t; +} __packed device_nvs_t; #endif /* _SOC_DEVICE_NVS_H_ */ diff --git a/src/soc/intel/braswell/include/soc/gpio.h b/src/soc/intel/braswell/include/soc/gpio.h index 4abc9f47bf..294f176676 100644 --- a/src/soc/intel/braswell/include/soc/gpio.h +++ b/src/soc/intel/braswell/include/soc/gpio.h @@ -18,6 +18,7 @@ #define _SOC_GPIO_H_ #include <stdint.h> +#include <compiler.h> #include <arch/io.h> #include <soc/gpio_defs.h> #include <soc/iomap.h> @@ -394,7 +395,7 @@ struct soc_gpio_map { u32 wake_mask:1; u32 is_gpio:1; u32 skip_config:1; -} __attribute__ ((packed)); +} __packed; struct soc_gpio_config { const struct soc_gpio_map *north; diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h index d3dfd28320..80b0759d76 100644 --- a/src/soc/intel/braswell/include/soc/nvs.h +++ b/src/soc/intel/braswell/include/soc/nvs.h @@ -19,6 +19,7 @@ #define _SOC_NVS_H_ #include <rules.h> +#include <compiler.h> #include <vendorcode/google/chromeos/gnvs.h> #include <soc/device_nvs.h> @@ -68,7 +69,7 @@ typedef struct { /* LPSS (0x1000) */ device_nvs_t dev; -} __attribute__((packed)) global_nvs_t; +} __packed global_nvs_t; void acpi_create_gnvs(global_nvs_t *gnvs); #if ENV_SMM diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h index 3d11330efb..5f809edecd 100644 --- a/src/soc/intel/braswell/include/soc/pm.h +++ b/src/soc/intel/braswell/include/soc/pm.h @@ -17,6 +17,7 @@ #ifndef _SOC_PM_H_ #define _SOC_PM_H_ +#include <compiler.h> #include <arch/acpi.h> #define IOCOM1 0x3f8 @@ -221,7 +222,7 @@ struct chipset_power_state { uint32_t gen_pmcon1; uint32_t gen_pmcon2; int prev_sleep_state; -} __attribute__((packed)); +} __packed; struct chipset_power_state *fill_power_state(void); diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c index 4bdcdbff8f..3fc9ba1114 100644 --- a/src/soc/intel/braswell/spi.c +++ b/src/soc/intel/braswell/spi.c @@ -26,6 +26,7 @@ #include <spi_flash.h> #include <spi-generic.h> #include <stdint.h> +#include <compiler.h> #include <stdlib.h> #include <string.h> @@ -80,7 +81,7 @@ typedef struct ich9_spi_regs { uint16_t preop; uint16_t optype; uint8_t opmenu[8]; -} __attribute__((packed)) ich9_spi_regs; +} __packed ich9_spi_regs; typedef struct ich_spi_controller { int locked; diff --git a/src/soc/intel/broadwell/include/soc/device_nvs.h b/src/soc/intel/broadwell/include/soc/device_nvs.h index a436a4c661..15240d13b4 100644 --- a/src/soc/intel/broadwell/include/soc/device_nvs.h +++ b/src/soc/intel/broadwell/include/soc/device_nvs.h @@ -17,6 +17,7 @@ #define _BROADWELL_DEVICE_NVS_H_ #include <stdint.h> +#include <compiler.h> /* Offset in Global NVS where this structure lives */ #define DEVICE_NVS_OFFSET 0x1000 @@ -35,6 +36,6 @@ typedef struct { u8 enable[9]; u32 bar0[9]; u32 bar1[9]; -} __attribute__((packed)) device_nvs_t; +} __packed device_nvs_t; #endif diff --git a/src/soc/intel/broadwell/include/soc/gpio.h b/src/soc/intel/broadwell/include/soc/gpio.h index 7aba8dcf60..c8f0300f15 100644 --- a/src/soc/intel/broadwell/include/soc/gpio.h +++ b/src/soc/intel/broadwell/include/soc/gpio.h @@ -17,6 +17,7 @@ #define _BROADWELL_GPIO_H_ #include <stdint.h> +#include <compiler.h> #define CROS_GPIO_DEVICE_NAME "PCH-LP" #define CROS_GPIO_ACPI_DEVICE_NAME "INT3437:00" @@ -167,7 +168,7 @@ struct gpio_config { u8 reset; u8 blink; u8 pirq; -} __attribute__ ((packed)); +} __packed; /* Configure GPIOs with mainboard provided settings */ void init_one_gpio(int gpio_num, struct gpio_config *config); diff --git a/src/soc/intel/broadwell/include/soc/me.h b/src/soc/intel/broadwell/include/soc/me.h index 0d0ad7b3d4..34b44816e8 100644 --- a/src/soc/intel/broadwell/include/soc/me.h +++ b/src/soc/intel/broadwell/include/soc/me.h @@ -16,6 +16,7 @@ #ifndef _BROADWELL_ME_H_ #define _BROADWELL_ME_H_ +#include <compiler.h> #include <commonlib/loglevel.h> #define ME_RETRY 100000 /* 1 second */ @@ -75,7 +76,7 @@ struct me_hfs { u32 boot_options_present: 1; u32 ack_data: 3; u32 bios_msg_ack: 4; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_UMA 0x44 @@ -85,7 +86,7 @@ struct me_uma { u32 valid: 1; u32 reserved_0: 14; u32 set_to_one: 1; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_H_GS 0x4c #define ME_INIT_DONE 1 @@ -104,7 +105,7 @@ struct me_did { u32 rapid_start: 1; u32 status: 4; u32 init_done: 4; -} __attribute__ ((packed)); +} __packed; /* * Apparently the GMES register is renamed to HFS2 (or HFSTS2 according @@ -195,7 +196,7 @@ struct me_hfs2 { u32 current_state: 8; u32 current_pmevent: 4; u32 progress_code: 4; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_HFS5 0x68 @@ -212,7 +213,7 @@ struct me_heres { u32 reserved: 26; u32 extend_feature_present: 1; u32 extend_reg_valid: 1; -} __attribute__ ((packed)); +} __packed; /* * Management Engine MEI registers @@ -233,7 +234,7 @@ struct mei_csr { u32 buffer_read_ptr: 8; u32 buffer_write_ptr: 8; u32 buffer_depth: 8; -} __attribute__ ((packed)); +} __packed; #define MEI_ADDRESS_CORE 0x01 #define MEI_ADDRESS_AMT 0x02 @@ -251,7 +252,7 @@ struct mei_header { u32 length: 9; u32 reserved: 6; u32 is_complete: 1; -} __attribute__ ((packed)); +} __packed; #define MKHI_GROUP_ID_CBM 0x00 #define MKHI_GLOBAL_RESET 0x0b @@ -274,7 +275,7 @@ struct mkhi_header { u32 is_response: 1; u32 reserved: 8; u32 result: 8; -} __attribute__ ((packed)); +} __packed; struct me_fw_version { u16 code_minor; @@ -285,7 +286,7 @@ struct me_fw_version { u16 recovery_major; u16 recovery_build_number; u16 recovery_hot_fix; -} __attribute__ ((packed)); +} __packed; /* ICC Messages */ #define ICC_SET_CLOCK_ENABLES 0x3 @@ -297,14 +298,14 @@ struct icc_header { u32 icc_status; u32 length; u32 reserved; -} __attribute__ ((packed)); +} __packed; struct icc_clock_enables_msg { u32 clock_enables; u32 clock_mask; u32 no_response: 1; u32 reserved: 31; -} __attribute__ ((packed)); +} __packed; #define HECI_EOP_STATUS_SUCCESS 0x0 #define HECI_EOP_PERFORM_GLOBAL_RESET 0x1 @@ -318,7 +319,7 @@ struct icc_clock_enables_msg { struct me_global_reset { u8 request_origin; u8 reset_type; -} __attribute__ ((packed)); +} __packed; typedef enum { ME_NORMAL_BIOS_PATH, @@ -364,21 +365,21 @@ typedef struct { u32 mbp_size : 8; u32 num_entries : 8; u32 rsvd : 16; -} __attribute__ ((packed)) mbp_header; +} __packed mbp_header; typedef struct { u32 app_id : 8; u32 item_id : 8; u32 length : 8; u32 rsvd : 8; -} __attribute__ ((packed)) mbp_item_header; +} __packed mbp_item_header; typedef struct { u32 major_version : 16; u32 minor_version : 16; u32 hotfix_version : 16; u32 build_version : 16; -} __attribute__ ((packed)) mbp_fw_version_name; +} __packed mbp_fw_version_name; typedef struct { u32 full_net : 1; @@ -400,13 +401,13 @@ typedef struct { u32 reserved_4 : 1; u32 wlan : 1; u32 reserved_5 : 8; -} __attribute__ ((packed)) mbp_mefwcaps; +} __packed mbp_mefwcaps; typedef struct { u16 device_id; u16 fuse_test_flags; u32 umchid[4]; -} __attribute__ ((packed)) mbp_rom_bist_data; +} __packed mbp_rom_bist_data; typedef struct { u32 key[8]; @@ -424,7 +425,7 @@ typedef struct { u32 image_type: 4; u32 brand: 4; u32 rsvd1: 16; -} __attribute__ ((packed)) mbp_me_firmware_type; +} __packed mbp_me_firmware_type; typedef struct { mbp_me_firmware_type rule_data; @@ -434,7 +435,7 @@ typedef struct { typedef struct { u16 icc_start_address; u16 mask; -} __attribute__ ((packed)) icc_address_mask; +} __packed icc_address_mask; typedef struct { u8 num_icc_profiles; @@ -443,7 +444,7 @@ typedef struct { u8 reserved; u32 icc_reg_bundles; icc_address_mask icc_address_mask[0]; -} __attribute__ ((packed)) mbp_icc_profile; +} __packed mbp_icc_profile; typedef struct { u16 lock_state : 1; @@ -452,24 +453,24 @@ typedef struct { u16 flash_wear_out : 1; u16 flash_variable_security : 1; u16 reserved : 11; -} __attribute__ ((packed)) tdt_state_flag; +} __packed tdt_state_flag; typedef struct { u8 state; u8 last_theft_trigger; tdt_state_flag flags; -} __attribute__ ((packed)) mbp_at_state; +} __packed mbp_at_state; typedef struct { u32 wake_event_mrst_time_ms; u32 mrst_pltrst_time_ms; u32 pltrst_cpurst_time_ms; -} __attribute__ ((packed)) mbp_plat_time; +} __packed mbp_plat_time; typedef struct { u32 device_type : 2; u32 reserved : 30; -} __attribute__ ((packed)) mbp_nfc_data; +} __packed mbp_nfc_data; typedef struct { mbp_fw_version_name *fw_version_name; @@ -489,7 +490,7 @@ struct me_fwcaps { u8 length; mbp_mefwcaps caps_sku; u8 reserved[3]; -} __attribute__ ((packed)); +} __packed; void intel_me_hsio_version(uint16_t *version, uint16_t *checksum); diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h index 55d6c8b4ea..a7d6d7c9fc 100644 --- a/src/soc/intel/broadwell/include/soc/nvs.h +++ b/src/soc/intel/broadwell/include/soc/nvs.h @@ -17,6 +17,7 @@ #ifndef _BROADWELL_NVS_H_ #define _BROADWELL_NVS_H_ +#include <compiler.h> #include <vendorcode/google/chromeos/gnvs.h> #include <soc/device_nvs.h> @@ -56,7 +57,7 @@ typedef struct { /* Device specific (0x1000) */ device_nvs_t dev; -} __attribute__((packed)) global_nvs_t; +} __packed global_nvs_t; void acpi_create_gnvs(global_nvs_t *gnvs); #ifdef __SMM__ diff --git a/src/soc/intel/broadwell/include/soc/pei_data.h b/src/soc/intel/broadwell/include/soc/pei_data.h index 318cb882d8..339dadd4d6 100644 --- a/src/soc/intel/broadwell/include/soc/pei_data.h +++ b/src/soc/intel/broadwell/include/soc/pei_data.h @@ -30,6 +30,7 @@ #define PEI_DATA_H #include <types.h> +#include <compiler.h> #include <memory_info.h> #define PEI_VERSION 22 @@ -74,7 +75,7 @@ struct usb2_port_setting { uint8_t enable; uint8_t oc_pin; uint8_t location; -} __attribute__((packed)); +} __packed; struct usb3_port_setting { uint8_t enable; @@ -84,7 +85,7 @@ struct usb3_port_setting { * Set to 1 if trace length is <= 5 inches */ uint8_t fixed_eq; -} __attribute__((packed)); +} __packed; struct pei_data { uint32_t pei_version; @@ -191,7 +192,7 @@ struct pei_data { void *data_to_save; int data_to_save_size; struct memory_info meminfo; -} __attribute__((packed)); +} __packed; typedef struct pei_data PEI_DATA; diff --git a/src/soc/intel/broadwell/include/soc/smm.h b/src/soc/intel/broadwell/include/soc/smm.h index be7e24c087..9a749c9051 100644 --- a/src/soc/intel/broadwell/include/soc/smm.h +++ b/src/soc/intel/broadwell/include/soc/smm.h @@ -17,13 +17,14 @@ #define _BROADWELL_SMM_H_ #include <stdint.h> +#include <compiler.h> #include <cpu/x86/msr.h> struct ied_header { char signature[10]; u32 size; u8 reserved[34]; -} __attribute__ ((packed)); +} __packed; struct smm_relocation_params { u32 smram_base; diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index a573e32981..eea3ade7f5 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -13,6 +13,7 @@ /* This file is derived from the flashrom project. */ #include <stdint.h> +#include <compiler.h> #include <stdlib.h> #include <string.h> #include <bootstate.h> @@ -92,7 +93,7 @@ typedef struct ich9_spi_regs { uint32_t srdl; uint32_t srdc; uint32_t srd; -} __attribute__((packed)) ich9_spi_regs; +} __packed ich9_spi_regs; typedef struct ich_spi_controller { int locked; diff --git a/src/soc/intel/common/block/i2c/lpss_i2c.h b/src/soc/intel/common/block/i2c/lpss_i2c.h index 8a53660fbd..2cb3d5ed52 100644 --- a/src/soc/intel/common/block/i2c/lpss_i2c.h +++ b/src/soc/intel/common/block/i2c/lpss_i2c.h @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <compiler.h> #include <intelblocks/lpss_i2c.h> #define LPSS_DEBUG BIOS_NEVER @@ -65,7 +66,7 @@ struct lpss_i2c_regs { uint32_t comp_param1; uint32_t comp_version; uint32_t comp_type; -} __attribute__((packed)); +} __packed; /* Get I2C controller base address */ uintptr_t lpss_i2c_base_address(unsigned int bus); diff --git a/src/soc/intel/common/mma.c b/src/soc/intel/common/mma.c index a58fe221f8..541a7b4d43 100644 --- a/src/soc/intel/common/mma.c +++ b/src/soc/intel/common/mma.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <compiler.h> #include <bootstate.h> #include <cbfs.h> #include <cbmem.h> @@ -31,7 +32,7 @@ struct mma_data_container { uint32_t mma_signature; /* "MMAD" */ uint8_t mma_data[0]; /* Variable size, platform/run time dependent. */ -} __attribute__ ((packed)); +} __packed; /* * Format of the MMA test metadata file, stored under CBFS diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c index e0d4b7de01..3ad4cb0d6e 100644 --- a/src/soc/intel/common/mrc_cache.c +++ b/src/soc/intel/common/mrc_cache.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <compiler.h> #include <string.h> #include <boot_device.h> #include <bootstate.h> @@ -40,7 +41,7 @@ struct mrc_metadata { uint16_t data_checksum; uint16_t header_checksum; uint32_t version; -} __attribute__((packed)); +} __packed; enum result { UPDATE_FAILURE = -1, diff --git a/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h b/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h index 5c4e49bb80..5bafea6fd0 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h +++ b/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h @@ -17,6 +17,7 @@ #define _BAYTRAIL_DEVICE_NVS_H_ #include <stdint.h> +#include <compiler.h> /* Offset in Global NVS where this structure lives */ #define DEVICE_NVS_OFFSET 0x1000 @@ -59,6 +60,6 @@ typedef struct { /* Extra */ u32 lpe_fw; /* LPE Firmware */ u8 rsvd1[3930]; /* Add padding so sizeof(device_nvs_t) == 0x1000 */ -} __attribute__((packed)) device_nvs_t; +} __packed device_nvs_t; #endif diff --git a/src/soc/intel/fsp_baytrail/include/soc/gpio.h b/src/soc/intel/fsp_baytrail/include/soc/gpio.h index 165443e08a..02c226b1d7 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/gpio.h +++ b/src/soc/intel/fsp_baytrail/include/soc/gpio.h @@ -17,6 +17,7 @@ #define _BAYTRAIL_GPIO_H_ #include <stdint.h> +#include <compiler.h> #include <arch/io.h> #include <soc/iomap.h> @@ -328,7 +329,7 @@ struct soc_gpio_map { u32 smi : 1; u32 is_gpio : 1; u32 sci : 1; -} __attribute__ ((packed)); +} __packed; struct soc_gpio_config { const struct soc_gpio_map *ncore; diff --git a/src/soc/intel/fsp_baytrail/include/soc/nvs.h b/src/soc/intel/fsp_baytrail/include/soc/nvs.h index 17c60ddcf7..f0bf888add 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/nvs.h +++ b/src/soc/intel/fsp_baytrail/include/soc/nvs.h @@ -17,6 +17,7 @@ #ifndef _BAYTRAIL_NVS_H_ #define _BAYTRAIL_NVS_H_ +#include <compiler.h> #include <soc/device_nvs.h> typedef struct { @@ -62,7 +63,7 @@ typedef struct { /* Baytrail LPSS (0x1000) */ device_nvs_t dev; -} __attribute__((packed)) global_nvs_t; +} __packed global_nvs_t; void acpi_create_gnvs(global_nvs_t *gnvs); #ifdef __SMM__ diff --git a/src/soc/intel/fsp_baytrail/include/soc/pmc.h b/src/soc/intel/fsp_baytrail/include/soc/pmc.h index d5b1c44cc5..9bafdc2fcf 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/pmc.h +++ b/src/soc/intel/fsp_baytrail/include/soc/pmc.h @@ -17,6 +17,7 @@ #ifndef _BAYTRAIL_PMC_H_ #define _BAYTRAIL_PMC_H_ +#include <compiler.h> #include <arch/acpi.h> #define IOCOM1 0x3f8 @@ -264,7 +265,7 @@ struct chipset_power_state { uint32_t prsts; uint32_t gen_pmcon1; uint32_t gen_pmcon2; -} __attribute__((packed)); +} __packed; /* Power Management Utility Functions. */ uint16_t get_pmbase(void); diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c index 0a04b9ba5f..96e0671c4a 100644 --- a/src/soc/intel/fsp_baytrail/spi.c +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -16,6 +16,7 @@ /* This file is derived from the flashrom project. */ #include <stdint.h> +#include <compiler.h> #include <stdlib.h> #include <string.h> #include <commonlib/helpers.h> @@ -93,7 +94,7 @@ typedef struct ich9_spi_regs { uint32_t srdl; uint32_t srdc; uint32_t srd; -} __attribute__((packed)) ich9_spi_regs; +} __packed ich9_spi_regs; typedef struct ich_spi_controller { int locked; diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h index ab8ca8eb71..2a737aca18 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h @@ -18,13 +18,14 @@ #define _BROADWELL_SMM_H_ #include <stdint.h> +#include <compiler.h> #include <cpu/x86/msr.h> struct ied_header { char signature[10]; u32 size; u8 reserved[34]; -} __attribute__ ((packed)); +} __packed; struct smm_relocation_params { u32 smram_base; diff --git a/src/soc/intel/fsp_broadwell_de/spi.c b/src/soc/intel/fsp_broadwell_de/spi.c index b917142722..b87ae90bc5 100644 --- a/src/soc/intel/fsp_broadwell_de/spi.c +++ b/src/soc/intel/fsp_broadwell_de/spi.c @@ -16,6 +16,7 @@ /* This file is derived from the flashrom project. */ #include <stdint.h> +#include <compiler.h> #include <stdlib.h> #include <string.h> #include <delay.h> @@ -91,7 +92,7 @@ typedef struct ich9_spi_regs { uint32_t srdl; uint32_t srdc; uint32_t srd; -} __attribute__((packed)) ich9_spi_regs; +} __packed ich9_spi_regs; typedef struct ich_spi_controller { int locked; diff --git a/src/soc/intel/quark/include/soc/pei_wrapper.h b/src/soc/intel/quark/include/soc/pei_wrapper.h index 5328e76e06..9e63a72ead 100644 --- a/src/soc/intel/quark/include/soc/pei_wrapper.h +++ b/src/soc/intel/quark/include/soc/pei_wrapper.h @@ -31,6 +31,7 @@ #define _PEI_WRAPPER_H_ #include <types.h> +#include <compiler.h> #define PEI_VERSION 22 @@ -53,7 +54,7 @@ struct pei_data { /* Data from MRC that should be saved to flash */ void *data_to_save; int data_to_save_size; -} __attribute__((packed)); +} __packed; typedef struct pei_data PEI_DATA; diff --git a/src/soc/intel/quark/include/soc/pm.h b/src/soc/intel/quark/include/soc/pm.h index 55e5e956aa..ae19cc6c9d 100644 --- a/src/soc/intel/quark/include/soc/pm.h +++ b/src/soc/intel/quark/include/soc/pm.h @@ -18,11 +18,12 @@ #define _SOC_PM_H_ #include <stdint.h> +#include <compiler.h> #include <arch/acpi.h> struct chipset_power_state { uint32_t prev_sleep_state; -} __attribute__ ((packed)); +} __packed; struct chipset_power_state *get_power_state(void); #if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) diff --git a/src/soc/intel/sch/nvs.h b/src/soc/intel/sch/nvs.h index 88c4998094..f62715ef92 100644 --- a/src/soc/intel/sch/nvs.h +++ b/src/soc/intel/sch/nvs.h @@ -16,6 +16,7 @@ #ifndef SOC_INTEL_SCH_NVS_H #define SOC_INTEL_SCH_NVS_H +#include <compiler.h> typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ @@ -133,7 +134,7 @@ typedef struct { u8 dock; /* 0xf0 - Docking Status */ u8 bten; u8 rsvd13[14]; -} __attribute__((packed)) global_nvs_t; +} __packed global_nvs_t; void acpi_create_gnvs(global_nvs_t * gnvs); diff --git a/src/soc/intel/sch/raminit.h b/src/soc/intel/sch/raminit.h index 4a81ec1580..0d4f436726 100644 --- a/src/soc/intel/sch/raminit.h +++ b/src/soc/intel/sch/raminit.h @@ -16,6 +16,8 @@ #ifndef RAMINIT_H #define RAMINIT_H +#include <compiler.h> + /** * Bit Equates **/ @@ -171,7 +173,7 @@ struct sys_info { u8 ram_param_source; /*DRAM Parameter Source SPD/SoftStraps(R) Block (down memory) */ u8 boot_path; -} __attribute__ ((packed)); +} __packed; void sdram_initialize(int boot_mode); diff --git a/src/soc/intel/skylake/include/soc/device_nvs.h b/src/soc/intel/skylake/include/soc/device_nvs.h index 79b516d9b5..02c9e65809 100644 --- a/src/soc/intel/skylake/include/soc/device_nvs.h +++ b/src/soc/intel/skylake/include/soc/device_nvs.h @@ -18,6 +18,7 @@ #define _SOC_DEVICE_NVS_H_ #include <stdint.h> +#include <compiler.h> /* Offset in Global NVS where this structure lives */ #define DEVICE_NVS_OFFSET 0x1000 @@ -38,6 +39,6 @@ typedef struct { u8 enable[11]; u32 bar0[11]; u32 bar1[11]; -} __attribute__((packed)) device_nvs_t; +} __packed device_nvs_t; #endif diff --git a/src/soc/intel/skylake/include/soc/me.h b/src/soc/intel/skylake/include/soc/me.h index 2736d1a04f..e88711ddf3 100644 --- a/src/soc/intel/skylake/include/soc/me.h +++ b/src/soc/intel/skylake/include/soc/me.h @@ -18,6 +18,8 @@ #ifndef _SKYLAKE_ME_H_ #define _SKYLAKE_ME_H_ +#include <compiler.h> + /* * Management Engine PCI registers */ @@ -68,7 +70,7 @@ union me_hfs { u32 current_power_source: 2; u32 d3_support_valid: 1; u32 d0i3_support_valid: 1; - } __attribute__ ((packed)) fields; + } __packed fields; }; #define PCI_ME_HFSTS2 0x48 @@ -166,7 +168,7 @@ union me_hfs2 { u32 current_state: 8; u32 current_pmevent: 4; u32 progress_code: 4; - } __attribute__ ((packed)) fields; + } __packed fields; }; #define PCI_ME_HFSTS3 0x60 @@ -183,7 +185,7 @@ union me_hfs3 { u32 reserved2: 21; u32 encrypt_key_override: 1; u32 power_down_mitigation: 1; - } __attribute__ ((packed)) fields; + } __packed fields; }; #define PCI_ME_HFSTS6 0x6c @@ -195,7 +197,7 @@ union me_hfs6 { struct { u32 reserved1: 30; u32 fpf_nvars: 2; - } __attribute__ ((packed)) fields; + } __packed fields; }; /* @@ -216,7 +218,7 @@ union host_csr { u32 host_read_offset: 8; u32 host_write_offset: 8; u32 me_cir_depth: 8; - } __attribute__ ((packed)) fields; + } __packed fields; }; #define MMIO_ME_CB_RW 0x08 @@ -234,7 +236,7 @@ union me_csr { u32 me_read_offset: 8; u32 me_write_offset: 8; u32 me_cir_buff: 8; - } __attribute__ ((packed)) fields; + } __packed fields; }; #define MMIO_ME_D0I3 0x800 @@ -265,7 +267,7 @@ union mei_header { u32 length: 9; u32 reserved: 6; u32 is_complete: 1; - } __attribute__ ((packed)) fields; + } __packed fields; }; void intel_me_status(void); diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index f72616f05e..4ca3d227b0 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -19,6 +19,7 @@ #define _SOC_NVS_H_ #include <rules.h> +#include <compiler.h> #include <vendorcode/google/chromeos/gnvs.h> typedef struct { @@ -60,7 +61,7 @@ typedef struct { /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; -} __attribute__((packed)) global_nvs_t; +} __packed global_nvs_t; #if ENV_SMM /* Used in SMM to find the ACPI GNVS address */ diff --git a/src/soc/intel/skylake/include/soc/pei_data.h b/src/soc/intel/skylake/include/soc/pei_data.h index be8ba79b92..58485837c6 100644 --- a/src/soc/intel/skylake/include/soc/pei_data.h +++ b/src/soc/intel/skylake/include/soc/pei_data.h @@ -31,6 +31,7 @@ #define _PEI_DATA_H_ #include <types.h> +#include <compiler.h> #define PEI_VERSION 22 @@ -92,7 +93,7 @@ struct pei_data { void *data_to_save; int data_to_save_size; int mem_cfg_id; -} __attribute__((packed)); +} __packed; typedef struct pei_data PEI_DATA; diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 15c291cc96..67b1f438b6 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -17,6 +17,7 @@ #ifndef _SOC_PM_H_ #define _SOC_PM_H_ +#include <compiler.h> #include <arch/acpi.h> #include <arch/io.h> #include <soc/pmc.h> @@ -147,7 +148,7 @@ struct chipset_power_state { uint32_t gen_pmcon_b; uint32_t gblrst_cause[2]; uint32_t prev_sleep_state; -} __attribute__ ((packed)); +} __packed; struct chipset_power_state *fill_power_state(void); diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h index 6ba6fdb72c..06c4aacd3d 100644 --- a/src/soc/intel/skylake/include/soc/smm.h +++ b/src/soc/intel/skylake/include/soc/smm.h @@ -18,6 +18,7 @@ #define _SOC_SMM_H_ #include <stdint.h> +#include <compiler.h> #include <cpu/x86/msr.h> #include <fsp/memmap.h> #include <soc/gpio.h> @@ -26,7 +27,7 @@ struct ied_header { char signature[10]; u32 size; u8 reserved[34]; -} __attribute__ ((packed)); +} __packed; struct smm_relocation_params { u32 smram_base; diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index 1865c00f7e..bf826ede77 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -20,6 +20,7 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <stdint.h> +#include <compiler.h> #include <stdlib.h> #include <string.h> #include <soc/iomap.h> @@ -650,7 +651,7 @@ static int send_heci_reset_message(void) u8 command; u8 reserved; u8 result; - } __attribute__ ((packed)) reply; + } __packed reply; struct reset_message { u8 group_id; u8 cmd; @@ -658,7 +659,7 @@ static int send_heci_reset_message(void) u8 result; u8 req_origin; u8 reset_type; - } __attribute__ ((packed)); + } __packed; struct reset_message msg = { .cmd = MKHI_GLOBAL_RESET, .req_origin = GR_ORIGIN_BIOS_POST, diff --git a/src/soc/marvell/mvmap2315/include/soc/bdb.h b/src/soc/marvell/mvmap2315/include/soc/bdb.h index f182a44ad2..a3e3ca53da 100644 --- a/src/soc/marvell/mvmap2315/include/soc/bdb.h +++ b/src/soc/marvell/mvmap2315/include/soc/bdb.h @@ -17,6 +17,7 @@ #define __SOC_MARVELL_MVMAP2315_BDB_H__ #include <stdint.h> +#include <compiler.h> #define MVMAP2315_BDB_LCM_BASE 0xE0000000 @@ -41,7 +42,7 @@ struct bdb_header { u32 signed_size; u32 oem_area_0_size; u8 reserved0[8]; -} __attribute__ ((packed)); +} __packed; struct bdb_key { u32 struct_magic; @@ -54,7 +55,7 @@ struct bdb_key { u32 key_version; char description[128]; u8 key_data[]; -} __attribute__ ((packed)); +} __packed; struct bdb_sig { u32 struct_magic; @@ -67,7 +68,7 @@ struct bdb_sig { u32 signed_size; char description[128]; u8 sig_SOC_MARVELL_MVMAP2315_data[]; -} __attribute__ ((packed)); +} __packed; struct bdb_data { u32 struct_magic; @@ -82,7 +83,7 @@ struct bdb_data { u32 signed_size; u8 reserved1[8]; char description[128]; -} __attribute__ ((packed)); +} __packed; struct bdb_hash { u64 offset; @@ -92,7 +93,7 @@ struct bdb_hash { u8 reserved0[2]; u64 load_address; u8 digest[32]; -} __attribute__ ((packed)); +} __packed; struct bdb_pointer { struct bdb_header *bdb_h; @@ -104,7 +105,7 @@ struct bdb_pointer { u8 *oem_1; struct bdb_hash *bdb_hash; struct bdb_sig *bdb_s; -} __attribute__ ((packed)); +} __packed; void set_bdb_pointers(u8 *start_addr, struct bdb_pointer *bdb_in); struct bdb_hash *find_bdb_image(struct bdb_pointer *bdb_info, u32 image_type); diff --git a/src/soc/mediatek/mt8173/uart.c b/src/soc/mediatek/mt8173/uart.c index adc8074ac1..d0b140d14d 100644 --- a/src/soc/mediatek/mt8173/uart.c +++ b/src/soc/mediatek/mt8173/uart.c @@ -19,6 +19,7 @@ #include <console/uart.h> #include <drivers/uart/uart8250reg.h> #include <stdint.h> +#include <compiler.h> #include <soc/addressmap.h> @@ -56,7 +57,7 @@ struct mtk_uart { }; uint32_t autobaud_en; /* Enable auto baudrate. */ uint32_t highspeed; /* High speed UART. */ -} __attribute__ ((packed)); +} __packed; /* Peripheral Reset and Power Down registers */ struct mtk_peri_globalcon { @@ -75,7 +76,7 @@ struct mtk_peri_globalcon { uint32_t pdn_md1_sta; uint32_t pdn_md2_sta; uint32_t pdn_md_mask; -} __attribute__ ((packed)); +} __packed; static struct mtk_uart *const uart_ptr = (void *)UART0_BASE; diff --git a/src/soc/nvidia/tegra124/include/soc/clk_rst.h b/src/soc/nvidia/tegra124/include/soc/clk_rst.h index f7d78eee17..165b823145 100644 --- a/src/soc/nvidia/tegra124/include/soc/clk_rst.h +++ b/src/soc/nvidia/tegra124/include/soc/clk_rst.h @@ -14,8 +14,10 @@ #ifndef _TEGRA124_CLK_RST_H_ #define _TEGRA124_CLK_RST_H_ +#include <compiler.h> + /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ -struct __attribute__ ((__packed__)) clk_rst_ctlr { +struct __packed clk_rst_ctlr { u32 rst_src; /* _RST_SOURCE, 0x000 */ u32 rst_dev_l; /* _RST_DEVICES_L, 0x004 */ u32 rst_dev_h; /* _RST_DEVICES_H, 0x008 */ diff --git a/src/soc/nvidia/tegra124/include/soc/dma.h b/src/soc/nvidia/tegra124/include/soc/dma.h index 53edc92369..4d3e9f6608 100644 --- a/src/soc/nvidia/tegra124/include/soc/dma.h +++ b/src/soc/nvidia/tegra124/include/soc/dma.h @@ -17,6 +17,7 @@ #define __NVIDIA_TEGRA124_DMA_H__ #include <inttypes.h> +#include <compiler.h> #include <soc/addressmap.h> /* @@ -66,7 +67,7 @@ struct apb_dma { u32 chan_wt_reg2; /* 0x4c */ u32 chan_wr_reg3; /* 0x50 */ u32 channel_swid1; /* 0x54 */ -} __attribute__((packed)); +} __packed; check_member(apb_dma, channel_swid1, 0x54); /* @@ -164,7 +165,7 @@ struct apb_dma_channel_regs { u32 apb_seq; /* 0x1c */ u32 wcount; /* 0x20 */ u32 word_transfer; /* 0x24 */ -} __attribute__((packed)); +} __packed; check_member(apb_dma_channel_regs, word_transfer, 0x24); struct apb_dma_channel { diff --git a/src/soc/nvidia/tegra124/include/soc/emc.h b/src/soc/nvidia/tegra124/include/soc/emc.h index bae0068e4c..f1ff7f320d 100644 --- a/src/soc/nvidia/tegra124/include/soc/emc.h +++ b/src/soc/nvidia/tegra124/include/soc/emc.h @@ -17,6 +17,7 @@ #include <stddef.h> #include <stdint.h> +#include <compiler.h> enum { EMC_PIN_RESET_MASK = 1 << 8, @@ -313,7 +314,7 @@ struct tegra_emc_regs { uint32_t puterm_width; /* 0x56c */ uint32_t bgbias_ctl0; /* 0x570 */ uint32_t puterm_adj; /* 0x574 */ -} __attribute__((packed)); +} __packed; check_member(tegra_emc_regs, puterm_adj, 0x574); diff --git a/src/soc/nvidia/tegra124/include/soc/spi.h b/src/soc/nvidia/tegra124/include/soc/spi.h index a9ea4eadf9..c56b302339 100644 --- a/src/soc/nvidia/tegra124/include/soc/spi.h +++ b/src/soc/nvidia/tegra124/include/soc/spi.h @@ -17,6 +17,7 @@ #include <spi-generic.h> #include <soc/dma.h> #include <stddef.h> +#include <compiler.h> struct tegra_spi_regs { u32 command1; /* 0x000: SPI_COMMAND1 */ @@ -34,7 +35,7 @@ struct tegra_spi_regs { u32 rsvd2[31]; /* 0x10c-0x187 reserved */ u32 rx_fifo; /* 0x188: SPI_FIFO2 */ u32 spare_ctl; /* 0x18c: SPI_SPARE_CTRL */ -} __attribute__((packed)); +} __packed; check_member(tegra_spi_regs, spare_ctl, 0x18c); enum spi_xfer_mode { diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c index 2737b282e0..74d337caeb 100644 --- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c @@ -13,6 +13,7 @@ */ #include <stdint.h> +#include <compiler.h> /* Function unit addresses. */ enum { @@ -642,7 +643,7 @@ struct lp0_header { uint32_t destination; // Where to load the blob in iRAM. uint32_t entry_point; // Entry point for the blob. uint32_t code_length; // Length of just the data. -} __attribute__((packed)); +} __packed; struct lp0_header header __attribute__((section(".header"))) = { diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c index 1d4934b0a3..76ea4261a0 100644 --- a/src/soc/nvidia/tegra124/uart.c +++ b/src/soc/nvidia/tegra124/uart.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <compiler.h> #include <arch/io.h> #include <boot/coreboot_tables.h> #include <console/console.h> /* for __console definition */ @@ -38,7 +39,7 @@ struct tegra124_uart { uint32_t mcr; // Modem control register. uint32_t lsr; // Line status register. uint32_t msr; // Modem status register. -} __attribute__ ((packed)); +} __packed; static void tegra124_uart_tx_flush(struct tegra124_uart *uart_ptr); static int tegra124_uart_tst_byte(struct tegra124_uart *uart_ptr); diff --git a/src/soc/nvidia/tegra210/include/soc/clk_rst.h b/src/soc/nvidia/tegra210/include/soc/clk_rst.h index 9c62e6115c..65fb8fe7c9 100644 --- a/src/soc/nvidia/tegra210/include/soc/clk_rst.h +++ b/src/soc/nvidia/tegra210/include/soc/clk_rst.h @@ -15,9 +15,10 @@ #define _TEGRA210_CLK_RST_H_ #include <stdint.h> #include <stddef.h> +#include <compiler.h> /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ -struct __attribute__ ((__packed__)) clk_rst_ctlr { +struct __packed clk_rst_ctlr { u32 rst_src; /* _RST_SOURCE, 0x000 */ u32 rst_dev_l; /* _RST_DEVICES_L, 0x004 */ u32 rst_dev_h; /* _RST_DEVICES_H, 0x008 */ diff --git a/src/soc/nvidia/tegra210/include/soc/clst_clk.h b/src/soc/nvidia/tegra210/include/soc/clst_clk.h index 89690f8b55..1524a9e900 100644 --- a/src/soc/nvidia/tegra210/include/soc/clst_clk.h +++ b/src/soc/nvidia/tegra210/include/soc/clst_clk.h @@ -14,8 +14,10 @@ #ifndef _TEGRA210_CLST_CLK_H_ #define _TEGRA210_CLST_CLK_H_ +#include <compiler.h> + /* Cluster Clock (CLUSTER_CLOCKS_PUBLIC_) regs */ -struct __attribute__ ((__packed__)) clst_clk_ctlr { +struct __packed clst_clk_ctlr { u32 pllx_base; /* _PLLX_BASE, 0x000 */ u32 pllx_misc; /* _PLLX_MISC, 0x004 */ u32 pllx_misc1; /* _PLLX_MISC_1, 0x008 */ diff --git a/src/soc/nvidia/tegra210/include/soc/dma.h b/src/soc/nvidia/tegra210/include/soc/dma.h index 66db52a331..a4a9213a84 100644 --- a/src/soc/nvidia/tegra210/include/soc/dma.h +++ b/src/soc/nvidia/tegra210/include/soc/dma.h @@ -16,6 +16,7 @@ #define __NVIDIA_TEGRA210_DMA_H__ #include <inttypes.h> +#include <compiler.h> #include <soc/addressmap.h> /* @@ -65,7 +66,7 @@ struct apb_dma { u32 chan_wt_reg2; /* 0x4c */ u32 chan_wr_reg3; /* 0x50 */ u32 channel_swid1; /* 0x54 */ -} __attribute__((packed)); +} __packed; check_member(apb_dma, channel_swid1, 0x54); /* Security enable for DMA channel */ @@ -166,7 +167,7 @@ struct apb_dma_channel_regs { u32 apb_seq; /* 0x1c */ u32 wcount; /* 0x20 */ u32 word_transfer; /* 0x24 */ -} __attribute__((packed)); +} __packed; check_member(apb_dma_channel_regs, word_transfer, 0x24); struct apb_dma_channel { diff --git a/src/soc/nvidia/tegra210/include/soc/emc.h b/src/soc/nvidia/tegra210/include/soc/emc.h index 09bc7c64f0..9e52b6969e 100644 --- a/src/soc/nvidia/tegra210/include/soc/emc.h +++ b/src/soc/nvidia/tegra210/include/soc/emc.h @@ -17,6 +17,7 @@ #include <stddef.h> #include <stdint.h> +#include <compiler.h> enum { EMC_PIN_RESET_MASK = 1 << 8, @@ -465,7 +466,7 @@ struct tegra_emc_regs { uint32_t pmacro_ib_rxrt; /* 0xCF4 */ uint32_t pmacro_training_ctrl0; /* 0xCF8 */ uint32_t pmacro_training_ctrl1; /* 0xCFC */ -} __attribute__((packed)); +} __packed; check_member(tegra_emc_regs, pmacro_training_ctrl1, 0xCFC); diff --git a/src/soc/nvidia/tegra210/include/soc/spi.h b/src/soc/nvidia/tegra210/include/soc/spi.h index 49f786855f..188fa665db 100644 --- a/src/soc/nvidia/tegra210/include/soc/spi.h +++ b/src/soc/nvidia/tegra210/include/soc/spi.h @@ -15,6 +15,7 @@ #ifndef __NVIDIA_TEGRA210_SPI_H__ #define __NVIDIA_TEGRA210_SPI_H__ +#include <compiler.h> #include <soc/dma.h> #include <spi-generic.h> #include <stddef.h> @@ -35,7 +36,7 @@ struct tegra_spi_regs { u32 rsvd2[31]; /* 0x10c-0x187 reserved */ u32 rx_fifo; /* 0x188: SPI_FIFO2 */ u32 spare_ctl; /* 0x18c: SPI_SPARE_CTRL */ -} __attribute__((packed)); +} __packed; check_member(tegra_spi_regs, spare_ctl, 0x18c); enum spi_xfer_mode { diff --git a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c index d3ac67b00f..a6d9533ffa 100644 --- a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c @@ -13,6 +13,7 @@ */ #include <stdint.h> +#include <compiler.h> /* Function unit addresses. */ enum { @@ -1118,7 +1119,7 @@ struct lp0_header { uint32_t destination; // Where to load the blob in iRAM. uint32_t entry_point; // Entry point for the blob. uint32_t code_length; // Length of just the data. -} __attribute__((packed)); +} __packed; struct lp0_header header __attribute__((section(".header"))) = { diff --git a/src/soc/nvidia/tegra210/uart.c b/src/soc/nvidia/tegra210/uart.c index 1f16067049..608b443dea 100644 --- a/src/soc/nvidia/tegra210/uart.c +++ b/src/soc/nvidia/tegra210/uart.c @@ -19,6 +19,7 @@ #include <console/uart.h> #include <drivers/uart/uart8250reg.h> #include <stdint.h> +#include <compiler.h> struct tegra210_uart { union { @@ -38,7 +39,7 @@ struct tegra210_uart { uint32_t mcr; // Modem control register. uint32_t lsr; // Line status register. uint32_t msr; // Modem status register. -} __attribute__ ((packed)); +} __packed; static struct tegra210_uart * const uart_ptr = diff --git a/src/soc/qualcomm/ipq40xx/include/soc/cdp.h b/src/soc/qualcomm/ipq40xx/include/soc/cdp.h index 1fa9fc45e3..dbff384cd7 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/cdp.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/cdp.h @@ -32,6 +32,7 @@ #define _IPQ40XX_CDP_H_ #include <types.h> +#include <compiler.h> unsigned smem_get_board_machtype(void); @@ -150,7 +151,7 @@ typedef struct { flash_desc flashdesc; spinorflash_params_t flash_param; #endif -} __attribute__ ((__packed__)) board_ipq40xx_params_t; +} __packed board_ipq40xx_params_t; extern board_ipq40xx_params_t *gboard_param; diff --git a/src/soc/qualcomm/ipq40xx/lcc.c b/src/soc/qualcomm/ipq40xx/lcc.c index da9d5ae983..5d3738c1af 100644 --- a/src/soc/qualcomm/ipq40xx/lcc.c +++ b/src/soc/qualcomm/ipq40xx/lcc.c @@ -29,6 +29,7 @@ #include <stdlib.h> #include <stdint.h> +#include <compiler.h> #include <delay.h> #include <console/console.h> #include <soc/clock.h> @@ -43,11 +44,11 @@ typedef struct { void *lcc_pll_regs; } IpqLccClocks; -typedef struct __attribute__((packed)) { +typedef struct __packed { uint32_t apcs; } IpqLccGccRegs; -typedef struct __attribute__((packed)) { +typedef struct __packed { uint32_t mode; uint32_t l_val; uint32_t m_val; @@ -57,20 +58,20 @@ typedef struct __attribute__((packed)) { uint32_t status; } IpqLccPll0Regs; -typedef struct __attribute__((packed)) { +typedef struct __packed { uint32_t ns; uint32_t md; uint32_t UNUSED; uint32_t status; } IpqLccAhbixRegs; -typedef struct __attribute__((packed)) { +typedef struct __packed { uint32_t ns; uint32_t md; uint32_t status; } IpqLccMi2sRegs; -typedef struct __attribute__((packed)) { +typedef struct __packed { uint32_t pri; uint32_t sec; } IpqLccPllRegs; diff --git a/src/soc/qualcomm/ipq806x/include/soc/cdp.h b/src/soc/qualcomm/ipq806x/include/soc/cdp.h index b7498ce23c..bdfeb89403 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/cdp.h +++ b/src/soc/qualcomm/ipq806x/include/soc/cdp.h @@ -5,6 +5,7 @@ #define _IPQ806X_CDP_H_ #include <types.h> +#include <compiler.h> unsigned smem_get_board_machtype(void); @@ -123,7 +124,7 @@ typedef struct { flash_desc flashdesc; spinorflash_params_t flash_param; #endif -} __attribute__ ((__packed__)) board_ipq806x_params_t; +} __packed board_ipq806x_params_t; extern board_ipq806x_params_t *gboard_param; diff --git a/src/soc/qualcomm/ipq806x/lcc.c b/src/soc/qualcomm/ipq806x/lcc.c index d577487618..99994e928b 100644 --- a/src/soc/qualcomm/ipq806x/lcc.c +++ b/src/soc/qualcomm/ipq806x/lcc.c @@ -29,6 +29,7 @@ #include <stdlib.h> #include <stdint.h> +#include <compiler.h> #include <delay.h> #include <console/console.h> #include <soc/clock.h> @@ -43,11 +44,11 @@ typedef struct { void *lcc_pll_regs; } Ipq806xLccClocks; -typedef struct __attribute__((packed)) { +typedef struct __packed { uint32_t apcs; } Ipq806xLccGccRegs; -typedef struct __attribute__((packed)) { +typedef struct __packed { uint32_t mode; uint32_t l_val; uint32_t m_val; @@ -57,20 +58,20 @@ typedef struct __attribute__((packed)) { uint32_t status; } Ipq806xLccPll0Regs; -typedef struct __attribute__((packed)) { +typedef struct __packed { uint32_t ns; uint32_t md; uint32_t UNUSED; uint32_t status; } Ipq806xLccAhbixRegs; -typedef struct __attribute__((packed)) { +typedef struct __packed { uint32_t ns; uint32_t md; uint32_t status; } Ipq806xLccMi2sRegs; -typedef struct __attribute__((packed)) { +typedef struct __packed { uint32_t pri; uint32_t sec; } Ipq806xLccPllRegs; diff --git a/src/soc/samsung/exynos5250/i2c.c b/src/soc/samsung/exynos5250/i2c.c index 97db093119..2f3f28fb2b 100644 --- a/src/soc/samsung/exynos5250/i2c.c +++ b/src/soc/samsung/exynos5250/i2c.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <compiler.h> #include <arch/io.h> #include <assert.h> #include <console/console.h> @@ -23,7 +24,7 @@ #include <soc/i2c.h> #include <soc/periph.h> -struct __attribute__ ((packed)) i2c_regs +struct __packed i2c_regs { uint8_t con; uint8_t _1[3]; diff --git a/src/soc/samsung/exynos5250/include/soc/power.h b/src/soc/samsung/exynos5250/include/soc/power.h index 14553f9f29..dbcc4fe7a5 100644 --- a/src/soc/samsung/exynos5250/include/soc/power.h +++ b/src/soc/samsung/exynos5250/include/soc/power.h @@ -18,6 +18,7 @@ #ifndef CPU_SAMSUNG_EXYNOS5250_POWER_H #define CPU_SAMSUNG_EXYNOS5250_POWER_H +#include <compiler.h> #include <soc/cpu.h> /* Enable HW thermal trip with PS_HOLD_CONTROL register ENABLE_HW_TRIP bit */ @@ -59,7 +60,7 @@ struct exynos5_power { uint32_t padret_uart_opt; /* 0x3128 */ uint8_t reserved8[0x1e0]; uint32_t ps_hold_ctrl; /* 0x330c */ -} __attribute__ ((__packed__)); +} __packed; check_member(exynos5_power, ps_hold_ctrl, 0x330c); static struct exynos5_power * const exynos_power = (void*)EXYNOS5_POWER_BASE; diff --git a/src/soc/samsung/exynos5420/i2c.c b/src/soc/samsung/exynos5420/i2c.c index 877afab6ab..9a9b197cc5 100644 --- a/src/soc/samsung/exynos5420/i2c.c +++ b/src/soc/samsung/exynos5420/i2c.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <compiler.h> #include <arch/io.h> #include <assert.h> #include <console/console.h> @@ -26,7 +27,7 @@ #include <stddef.h> #include <timer.h> -struct __attribute__ ((packed)) i2c_regs +struct __packed i2c_regs { uint8_t con; uint8_t _1[3]; @@ -40,7 +41,7 @@ struct __attribute__ ((packed)) i2c_regs uint8_t _5[3]; }; -struct __attribute__ ((packed)) hsi2c_regs +struct __packed hsi2c_regs { uint32_t usi_ctl; uint32_t usi_fifo_ctl; diff --git a/src/soc/samsung/exynos5420/include/soc/dmc.h b/src/soc/samsung/exynos5420/include/soc/dmc.h index ef0198c92f..b19b660936 100644 --- a/src/soc/samsung/exynos5420/include/soc/dmc.h +++ b/src/soc/samsung/exynos5420/include/soc/dmc.h @@ -14,6 +14,8 @@ #ifndef CPU_SAMSUNG_EXYNOS5420_DMC_H #define CPU_SAMSUNG_EXYNOS5420_DMC_H +#include <compiler.h> + #define DMC_INTERLEAVE_SIZE 0x1f #define PAD_RETENTION_DRAM_COREBLK_VAL 0x10000000 @@ -201,7 +203,7 @@ struct exynos5_dmc { uint32_t pmcnt2_ppc; uint8_t res41[0xc]; uint32_t pmcnt3_ppc; /* 0xe140 */ -} __attribute__((packed)); +} __packed; check_member(exynos5_dmc, pmcnt3_ppc, 0xe140); static struct exynos5_dmc * const exynos_drex0 = (void *)EXYNOS5420_DMC_DREXI_0; @@ -252,7 +254,7 @@ struct exynos5_phy_control { uint32_t phy_con40; uint32_t phy_con41; uint32_t phy_con42; -} __attribute__((packed)); +} __packed; check_member(exynos5_phy_control, phy_con42, 0xac); static struct exynos5_phy_control * const exynos_phy0_control = @@ -267,7 +269,7 @@ struct exynos5_tzasc { uint8_t res2[0x8]; uint32_t memconfig0; uint32_t memconfig1; -} __attribute__((packed)); +} __packed; static struct exynos5_tzasc * const exynos_tzasc0 = (void *)EXYNOS5420_DMC_TZASC_0; diff --git a/src/soc/samsung/exynos5420/include/soc/power.h b/src/soc/samsung/exynos5420/include/soc/power.h index 5920916b0e..4fb96fd941 100644 --- a/src/soc/samsung/exynos5420/include/soc/power.h +++ b/src/soc/samsung/exynos5420/include/soc/power.h @@ -18,6 +18,7 @@ #ifndef CPU_SAMSUNG_EXYNOS5420_POWER_H #define CPU_SAMSUNG_EXYNOS5420_POWER_H +#include <compiler.h> #include <soc/cpu.h> /* Enable HW thermal trip with PS_HOLD_CONTROL register ENABLE_HW_TRIP bit */ @@ -72,7 +73,7 @@ struct exynos5_power { uint32_t padret_dram_cblk_opt; /* 0x31e8 */ uint8_t reservedC[0x120]; uint32_t ps_hold_ctrl; /* 0x330c */ -} __attribute__ ((__packed__)); +} __packed; check_member(exynos5_power, ps_hold_ctrl, 0x330c); static struct exynos5_power * const exynos_power = (void*)EXYNOS5_POWER_BASE; diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index 6b8d654a18..f95a0b46a0 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -17,6 +17,8 @@ #ifndef _INTEL_ME_H #define _INTEL_ME_H +#include <compiler.h> + #define ME_RETRY 100000 /* 1 second */ #define ME_DELAY 10 /* 10 us */ @@ -75,7 +77,7 @@ struct me_hfs { u32 boot_options_present: 1; u32 ack_data: 3; u32 bios_msg_ack: 4; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_UMA 0x44 @@ -85,7 +87,7 @@ struct me_uma { u32 valid: 1; u32 reserved_0: 14; u32 set_to_one: 1; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_H_GS 0x4c #define ME_INIT_DONE 1 @@ -98,7 +100,7 @@ struct me_did { u32 reserved: 8; u32 status: 4; u32 init_done: 4; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_GMES 0x48 #define ME_GMES_PHASE_ROM 0 @@ -124,7 +126,7 @@ struct me_gmes { u32 current_state: 8; u32 current_pmevent: 4; u32 progress_code: 4; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_HERES 0xbc #define PCI_ME_EXT_SHA1 0x00 @@ -136,7 +138,7 @@ struct me_heres { u32 reserved: 26; u32 extend_feature_present: 1; u32 extend_reg_valid: 1; -} __attribute__ ((packed)); +} __packed; /* * Management Engine MEI registers @@ -157,7 +159,7 @@ struct mei_csr { u32 buffer_read_ptr: 8; u32 buffer_write_ptr: 8; u32 buffer_depth: 8; -} __attribute__ ((packed)); +} __packed; #define MEI_ADDRESS_CORE 0x01 #define MEI_ADDRESS_AMT 0x02 @@ -175,7 +177,7 @@ struct mei_header { u32 length: 9; u32 reserved: 6; u32 is_complete: 1; -} __attribute__ ((packed)); +} __packed; #define MKHI_GROUP_ID_CBM 0x00 #define MKHI_GROUP_ID_FWCAPS 0x03 @@ -198,7 +200,7 @@ struct mkhi_header { u32 is_response: 1; u32 reserved: 8; u32 result: 8; -} __attribute__ ((packed)); +} __packed; struct me_fw_version { u16 code_minor; @@ -209,7 +211,7 @@ struct me_fw_version { u16 recovery_major; u16 recovery_build_number; u16 recovery_hot_fix; -} __attribute__ ((packed)); +} __packed; #define HECI_EOP_STATUS_SUCCESS 0x0 @@ -224,7 +226,7 @@ struct me_fw_version { struct me_global_reset { u8 request_origin; u8 reset_type; -} __attribute__ ((packed)); +} __packed; typedef enum { ME_NORMAL_BIOS_PATH, @@ -254,7 +256,7 @@ typedef struct { u32 minor_version : 16; u32 hotfix_version : 16; u32 build_version : 16; -} __attribute__ ((packed)) mbp_fw_version_name; +} __packed mbp_fw_version_name; typedef struct { u8 num_icc_profiles; @@ -262,7 +264,7 @@ typedef struct { u8 icc_profile_index; u8 reserved; u32 register_lock_mask[3]; -} __attribute__ ((packed)) mbp_icc_profile; +} __packed mbp_icc_profile; typedef struct { u32 full_net : 1; @@ -285,7 +287,7 @@ typedef struct { u32 reserved_4 : 1; u32 wlan : 1; u32 reserved_5 : 8; -} __attribute__ ((packed)) mefwcaps_sku; +} __packed mefwcaps_sku; typedef struct { u16 lock_state : 1; @@ -296,13 +298,13 @@ typedef struct { u16 wwan3gpresent : 1; u16 wwan3goob : 1; u16 reserved : 9; -} __attribute__ ((packed)) tdt_state_flag; +} __packed tdt_state_flag; typedef struct { u8 state; u8 last_theft_trigger; tdt_state_flag flags; -} __attribute__ ((packed)) tdt_state_info; +} __packed tdt_state_info; typedef struct { u32 platform_target_usage_type : 4; @@ -312,7 +314,7 @@ typedef struct { u32 intel_me_fw_image_type : 4; u32 platform_brand : 4; u32 reserved_1 : 16; -} __attribute__ ((packed)) platform_type_rule_data; +} __packed platform_type_rule_data; typedef struct { mefwcaps_sku fw_capabilities; @@ -323,7 +325,7 @@ typedef struct { u16 device_id; u16 fuse_test_flags; u32 umchid[4]; -} __attribute__ ((packed)) mbp_rom_bist_data; +} __packed mbp_rom_bist_data; typedef struct { u32 key[8]; @@ -349,20 +351,20 @@ typedef struct { u32 mbp_size : 8; u32 num_entries : 8; u32 rsvd : 16; -} __attribute__ ((packed)) mbp_header; +} __packed mbp_header; typedef struct { u32 app_id : 8; u32 item_id : 8; u32 length : 8; u32 rsvd : 8; -} __attribute__ ((packed)) mbp_item_header; +} __packed mbp_item_header; struct me_fwcaps { u32 id; u8 length; mefwcaps_sku caps_sku; u8 reserved[3]; -} __attribute__ ((packed)); +} __packed; #endif /* _INTEL_ME_H */ diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index e71fedae91..51fc7bb1f4 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -15,6 +15,7 @@ */ #include <stdint.h> +#include <compiler.h> #include "vendorcode/google/chromeos/gnvs.h" typedef struct { /* Miscellaneous */ @@ -150,7 +151,7 @@ typedef struct { /* ChromeOS specific (starts at 0x100)*/ chromeos_acpi_t chromeos; -} __attribute__((packed)) global_nvs_t; +} __packed global_nvs_t; #ifdef __SMM__ /* Used in SMM to find the ACPI GNVS address */ diff --git a/src/southbridge/intel/common/gpio.h b/src/southbridge/intel/common/gpio.h index 7b42b0680f..8bd3b961b7 100644 --- a/src/southbridge/intel/common/gpio.h +++ b/src/southbridge/intel/common/gpio.h @@ -17,6 +17,7 @@ #define INTEL_COMMON_GPIO_H #include <stdint.h> +#include <compiler.h> /* LPC GPIO Base Address Register */ #define GPIO_BASE 0x48 @@ -91,7 +92,7 @@ struct pch_gpio_set1 { u32 gpio29 : 1; u32 gpio30 : 1; u32 gpio31 : 1; -} __attribute__ ((packed)); +} __packed; struct pch_gpio_set2 { u32 gpio32 : 1; @@ -126,7 +127,7 @@ struct pch_gpio_set2 { u32 gpio61 : 1; u32 gpio62 : 1; u32 gpio63 : 1; -} __attribute__ ((packed)); +} __packed; struct pch_gpio_set3 { u32 gpio64 : 1; @@ -141,7 +142,7 @@ struct pch_gpio_set3 { u32 gpio73 : 1; u32 gpio74 : 1; u32 gpio75 : 1; -} __attribute__ ((packed)); +} __packed; struct pch_gpio_map { struct { diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 13db224a97..4b9bd20b2d 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -18,6 +18,7 @@ #include <stdint.h> #include <stdlib.h> #include <string.h> +#include <compiler.h> #include <bootstate.h> #include <commonlib/helpers.h> #include <delay.h> @@ -82,7 +83,7 @@ typedef struct ich7_spi_regs { uint16_t preop; uint16_t optype; uint8_t opmenu[8]; -} __attribute__((packed)) ich7_spi_regs; +} __packed ich7_spi_regs; typedef struct ich9_spi_regs { uint32_t bfpr; @@ -115,7 +116,7 @@ typedef struct ich9_spi_regs { uint32_t srdl; uint32_t srdc; uint32_t srd; -} __attribute__((packed)) ich9_spi_regs; +} __packed ich9_spi_regs; typedef struct ich_spi_controller { int locked; diff --git a/src/southbridge/intel/fsp_bd82x6x/gpio.h b/src/southbridge/intel/fsp_bd82x6x/gpio.h index d2f0e50452..3279be8ee5 100644 --- a/src/southbridge/intel/fsp_bd82x6x/gpio.h +++ b/src/southbridge/intel/fsp_bd82x6x/gpio.h @@ -17,6 +17,8 @@ #ifndef INTEL_BD82X6X_GPIO_H #define INTEL_BD82X6X_GPIO_H +#include <compiler.h> + #define GPIO_MODE_NATIVE 0 #define GPIO_MODE_GPIO 1 #define GPIO_MODE_NONE 1 @@ -69,7 +71,7 @@ struct pch_gpio_set1 { u32 gpio29 : 1; u32 gpio30 : 1; u32 gpio31 : 1; -} __attribute__ ((packed)); +} __packed; struct pch_gpio_set2 { u32 gpio32 : 1; @@ -104,7 +106,7 @@ struct pch_gpio_set2 { u32 gpio61 : 1; u32 gpio62 : 1; u32 gpio63 : 1; -} __attribute__ ((packed)); +} __packed; struct pch_gpio_set3 { u32 gpio64 : 1; @@ -120,7 +122,7 @@ struct pch_gpio_set3 { u32 gpio74 : 1; u32 gpio75 : 1; u32 fill_bitfield : 20; -} __attribute__ ((packed)); +} __packed; struct pch_gpio_map { union { diff --git a/src/southbridge/intel/fsp_bd82x6x/me.h b/src/southbridge/intel/fsp_bd82x6x/me.h index 6b8d654a18..f95a0b46a0 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me.h +++ b/src/southbridge/intel/fsp_bd82x6x/me.h @@ -17,6 +17,8 @@ #ifndef _INTEL_ME_H #define _INTEL_ME_H +#include <compiler.h> + #define ME_RETRY 100000 /* 1 second */ #define ME_DELAY 10 /* 10 us */ @@ -75,7 +77,7 @@ struct me_hfs { u32 boot_options_present: 1; u32 ack_data: 3; u32 bios_msg_ack: 4; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_UMA 0x44 @@ -85,7 +87,7 @@ struct me_uma { u32 valid: 1; u32 reserved_0: 14; u32 set_to_one: 1; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_H_GS 0x4c #define ME_INIT_DONE 1 @@ -98,7 +100,7 @@ struct me_did { u32 reserved: 8; u32 status: 4; u32 init_done: 4; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_GMES 0x48 #define ME_GMES_PHASE_ROM 0 @@ -124,7 +126,7 @@ struct me_gmes { u32 current_state: 8; u32 current_pmevent: 4; u32 progress_code: 4; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_HERES 0xbc #define PCI_ME_EXT_SHA1 0x00 @@ -136,7 +138,7 @@ struct me_heres { u32 reserved: 26; u32 extend_feature_present: 1; u32 extend_reg_valid: 1; -} __attribute__ ((packed)); +} __packed; /* * Management Engine MEI registers @@ -157,7 +159,7 @@ struct mei_csr { u32 buffer_read_ptr: 8; u32 buffer_write_ptr: 8; u32 buffer_depth: 8; -} __attribute__ ((packed)); +} __packed; #define MEI_ADDRESS_CORE 0x01 #define MEI_ADDRESS_AMT 0x02 @@ -175,7 +177,7 @@ struct mei_header { u32 length: 9; u32 reserved: 6; u32 is_complete: 1; -} __attribute__ ((packed)); +} __packed; #define MKHI_GROUP_ID_CBM 0x00 #define MKHI_GROUP_ID_FWCAPS 0x03 @@ -198,7 +200,7 @@ struct mkhi_header { u32 is_response: 1; u32 reserved: 8; u32 result: 8; -} __attribute__ ((packed)); +} __packed; struct me_fw_version { u16 code_minor; @@ -209,7 +211,7 @@ struct me_fw_version { u16 recovery_major; u16 recovery_build_number; u16 recovery_hot_fix; -} __attribute__ ((packed)); +} __packed; #define HECI_EOP_STATUS_SUCCESS 0x0 @@ -224,7 +226,7 @@ struct me_fw_version { struct me_global_reset { u8 request_origin; u8 reset_type; -} __attribute__ ((packed)); +} __packed; typedef enum { ME_NORMAL_BIOS_PATH, @@ -254,7 +256,7 @@ typedef struct { u32 minor_version : 16; u32 hotfix_version : 16; u32 build_version : 16; -} __attribute__ ((packed)) mbp_fw_version_name; +} __packed mbp_fw_version_name; typedef struct { u8 num_icc_profiles; @@ -262,7 +264,7 @@ typedef struct { u8 icc_profile_index; u8 reserved; u32 register_lock_mask[3]; -} __attribute__ ((packed)) mbp_icc_profile; +} __packed mbp_icc_profile; typedef struct { u32 full_net : 1; @@ -285,7 +287,7 @@ typedef struct { u32 reserved_4 : 1; u32 wlan : 1; u32 reserved_5 : 8; -} __attribute__ ((packed)) mefwcaps_sku; +} __packed mefwcaps_sku; typedef struct { u16 lock_state : 1; @@ -296,13 +298,13 @@ typedef struct { u16 wwan3gpresent : 1; u16 wwan3goob : 1; u16 reserved : 9; -} __attribute__ ((packed)) tdt_state_flag; +} __packed tdt_state_flag; typedef struct { u8 state; u8 last_theft_trigger; tdt_state_flag flags; -} __attribute__ ((packed)) tdt_state_info; +} __packed tdt_state_info; typedef struct { u32 platform_target_usage_type : 4; @@ -312,7 +314,7 @@ typedef struct { u32 intel_me_fw_image_type : 4; u32 platform_brand : 4; u32 reserved_1 : 16; -} __attribute__ ((packed)) platform_type_rule_data; +} __packed platform_type_rule_data; typedef struct { mefwcaps_sku fw_capabilities; @@ -323,7 +325,7 @@ typedef struct { u16 device_id; u16 fuse_test_flags; u32 umchid[4]; -} __attribute__ ((packed)) mbp_rom_bist_data; +} __packed mbp_rom_bist_data; typedef struct { u32 key[8]; @@ -349,20 +351,20 @@ typedef struct { u32 mbp_size : 8; u32 num_entries : 8; u32 rsvd : 16; -} __attribute__ ((packed)) mbp_header; +} __packed mbp_header; typedef struct { u32 app_id : 8; u32 item_id : 8; u32 length : 8; u32 rsvd : 8; -} __attribute__ ((packed)) mbp_item_header; +} __packed mbp_item_header; struct me_fwcaps { u32 id; u8 length; mefwcaps_sku caps_sku; u8 reserved[3]; -} __attribute__ ((packed)); +} __packed; #endif /* _INTEL_ME_H */ diff --git a/src/southbridge/intel/fsp_bd82x6x/nvs.h b/src/southbridge/intel/fsp_bd82x6x/nvs.h index 83bc832733..fc843194a7 100644 --- a/src/southbridge/intel/fsp_bd82x6x/nvs.h +++ b/src/southbridge/intel/fsp_bd82x6x/nvs.h @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <compiler.h> #include "vendorcode/google/chromeos/gnvs.h" typedef struct { /* Miscellaneous */ @@ -146,7 +147,7 @@ typedef struct { /* ChromeOS specific (starts at 0x100)*/ chromeos_acpi_t chromeos; -} __attribute__((packed)) global_nvs_t; +} __packed global_nvs_t; #ifdef __SMM__ /* Used in SMM to find the ACPI GNVS address */ diff --git a/src/southbridge/intel/fsp_i89xx/gpio.h b/src/southbridge/intel/fsp_i89xx/gpio.h index ee5484d26b..b89ab3ed37 100644 --- a/src/southbridge/intel/fsp_i89xx/gpio.h +++ b/src/southbridge/intel/fsp_i89xx/gpio.h @@ -17,6 +17,8 @@ #ifndef INTEL_I89XX_GPIO_H #define INTEL_I89XX_GPIO_H +#include <compiler.h> + #define GPIO_MODE_NATIVE 0 #define GPIO_MODE_GPIO 1 #define GPIO_MODE_NONE 1 @@ -69,7 +71,7 @@ struct pch_gpio_set1 { u32 gpio29 : 1; u32 gpio30 : 1; u32 gpio31 : 1; -} __attribute__ ((packed)); +} __packed; struct pch_gpio_set2 { u32 gpio32 : 1; @@ -104,7 +106,7 @@ struct pch_gpio_set2 { u32 gpio61 : 1; u32 gpio62 : 1; u32 gpio63 : 1; -} __attribute__ ((packed)); +} __packed; struct pch_gpio_set3 { u32 gpio64 : 1; @@ -120,7 +122,7 @@ struct pch_gpio_set3 { u32 gpio74 : 1; u32 gpio75 : 1; u32 fill_bitfield : 20; -} __attribute__ ((packed)); +} __packed; struct pch_gpio_map { union { diff --git a/src/southbridge/intel/fsp_i89xx/me.h b/src/southbridge/intel/fsp_i89xx/me.h index 6b8d654a18..f95a0b46a0 100644 --- a/src/southbridge/intel/fsp_i89xx/me.h +++ b/src/southbridge/intel/fsp_i89xx/me.h @@ -17,6 +17,8 @@ #ifndef _INTEL_ME_H #define _INTEL_ME_H +#include <compiler.h> + #define ME_RETRY 100000 /* 1 second */ #define ME_DELAY 10 /* 10 us */ @@ -75,7 +77,7 @@ struct me_hfs { u32 boot_options_present: 1; u32 ack_data: 3; u32 bios_msg_ack: 4; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_UMA 0x44 @@ -85,7 +87,7 @@ struct me_uma { u32 valid: 1; u32 reserved_0: 14; u32 set_to_one: 1; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_H_GS 0x4c #define ME_INIT_DONE 1 @@ -98,7 +100,7 @@ struct me_did { u32 reserved: 8; u32 status: 4; u32 init_done: 4; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_GMES 0x48 #define ME_GMES_PHASE_ROM 0 @@ -124,7 +126,7 @@ struct me_gmes { u32 current_state: 8; u32 current_pmevent: 4; u32 progress_code: 4; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_HERES 0xbc #define PCI_ME_EXT_SHA1 0x00 @@ -136,7 +138,7 @@ struct me_heres { u32 reserved: 26; u32 extend_feature_present: 1; u32 extend_reg_valid: 1; -} __attribute__ ((packed)); +} __packed; /* * Management Engine MEI registers @@ -157,7 +159,7 @@ struct mei_csr { u32 buffer_read_ptr: 8; u32 buffer_write_ptr: 8; u32 buffer_depth: 8; -} __attribute__ ((packed)); +} __packed; #define MEI_ADDRESS_CORE 0x01 #define MEI_ADDRESS_AMT 0x02 @@ -175,7 +177,7 @@ struct mei_header { u32 length: 9; u32 reserved: 6; u32 is_complete: 1; -} __attribute__ ((packed)); +} __packed; #define MKHI_GROUP_ID_CBM 0x00 #define MKHI_GROUP_ID_FWCAPS 0x03 @@ -198,7 +200,7 @@ struct mkhi_header { u32 is_response: 1; u32 reserved: 8; u32 result: 8; -} __attribute__ ((packed)); +} __packed; struct me_fw_version { u16 code_minor; @@ -209,7 +211,7 @@ struct me_fw_version { u16 recovery_major; u16 recovery_build_number; u16 recovery_hot_fix; -} __attribute__ ((packed)); +} __packed; #define HECI_EOP_STATUS_SUCCESS 0x0 @@ -224,7 +226,7 @@ struct me_fw_version { struct me_global_reset { u8 request_origin; u8 reset_type; -} __attribute__ ((packed)); +} __packed; typedef enum { ME_NORMAL_BIOS_PATH, @@ -254,7 +256,7 @@ typedef struct { u32 minor_version : 16; u32 hotfix_version : 16; u32 build_version : 16; -} __attribute__ ((packed)) mbp_fw_version_name; +} __packed mbp_fw_version_name; typedef struct { u8 num_icc_profiles; @@ -262,7 +264,7 @@ typedef struct { u8 icc_profile_index; u8 reserved; u32 register_lock_mask[3]; -} __attribute__ ((packed)) mbp_icc_profile; +} __packed mbp_icc_profile; typedef struct { u32 full_net : 1; @@ -285,7 +287,7 @@ typedef struct { u32 reserved_4 : 1; u32 wlan : 1; u32 reserved_5 : 8; -} __attribute__ ((packed)) mefwcaps_sku; +} __packed mefwcaps_sku; typedef struct { u16 lock_state : 1; @@ -296,13 +298,13 @@ typedef struct { u16 wwan3gpresent : 1; u16 wwan3goob : 1; u16 reserved : 9; -} __attribute__ ((packed)) tdt_state_flag; +} __packed tdt_state_flag; typedef struct { u8 state; u8 last_theft_trigger; tdt_state_flag flags; -} __attribute__ ((packed)) tdt_state_info; +} __packed tdt_state_info; typedef struct { u32 platform_target_usage_type : 4; @@ -312,7 +314,7 @@ typedef struct { u32 intel_me_fw_image_type : 4; u32 platform_brand : 4; u32 reserved_1 : 16; -} __attribute__ ((packed)) platform_type_rule_data; +} __packed platform_type_rule_data; typedef struct { mefwcaps_sku fw_capabilities; @@ -323,7 +325,7 @@ typedef struct { u16 device_id; u16 fuse_test_flags; u32 umchid[4]; -} __attribute__ ((packed)) mbp_rom_bist_data; +} __packed mbp_rom_bist_data; typedef struct { u32 key[8]; @@ -349,20 +351,20 @@ typedef struct { u32 mbp_size : 8; u32 num_entries : 8; u32 rsvd : 16; -} __attribute__ ((packed)) mbp_header; +} __packed mbp_header; typedef struct { u32 app_id : 8; u32 item_id : 8; u32 length : 8; u32 rsvd : 8; -} __attribute__ ((packed)) mbp_item_header; +} __packed mbp_item_header; struct me_fwcaps { u32 id; u8 length; mefwcaps_sku caps_sku; u8 reserved[3]; -} __attribute__ ((packed)); +} __packed; #endif /* _INTEL_ME_H */ diff --git a/src/southbridge/intel/fsp_i89xx/nvs.h b/src/southbridge/intel/fsp_i89xx/nvs.h index 83bc832733..fc843194a7 100644 --- a/src/southbridge/intel/fsp_i89xx/nvs.h +++ b/src/southbridge/intel/fsp_i89xx/nvs.h @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <compiler.h> #include "vendorcode/google/chromeos/gnvs.h" typedef struct { /* Miscellaneous */ @@ -146,7 +147,7 @@ typedef struct { /* ChromeOS specific (starts at 0x100)*/ chromeos_acpi_t chromeos; -} __attribute__((packed)) global_nvs_t; +} __packed global_nvs_t; #ifdef __SMM__ /* Used in SMM to find the ACPI GNVS address */ diff --git a/src/southbridge/intel/fsp_rangeley/gpio.h b/src/southbridge/intel/fsp_rangeley/gpio.h index 8a0b578fe0..d8fbcb985d 100644 --- a/src/southbridge/intel/fsp_rangeley/gpio.h +++ b/src/southbridge/intel/fsp_rangeley/gpio.h @@ -17,6 +17,8 @@ #ifndef INTEL_RANGELEY_GPIO_H #define INTEL_RANGELEY_GPIO_H +#include <compiler.h> + #define GPIO_MODE_NATIVE 0 #define GPIO_MODE_GPIO 1 #define GPIO_MODE_NONE 1 @@ -72,14 +74,14 @@ struct soc_gpio { u32 gpio29 : 1; u32 gpio30 : 1; u32 gpio31 : 1; -} __attribute__ ((packed)); +} __packed; struct soc_cfio { u32 pad_conf_0; u32 pad_conf_1; u32 pad_val; u32 pad_dft; -} __attribute__ ((packed)); +} __packed; struct soc_gpio_map { /* GPIO core */ diff --git a/src/southbridge/intel/fsp_rangeley/nvs.h b/src/southbridge/intel/fsp_rangeley/nvs.h index 5449f9457f..fd3329051d 100644 --- a/src/southbridge/intel/fsp_rangeley/nvs.h +++ b/src/southbridge/intel/fsp_rangeley/nvs.h @@ -14,6 +14,8 @@ * GNU General Public License for more details. */ +#include <compiler.h> + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ @@ -143,7 +145,7 @@ typedef struct { u8 mmio; /* 0xf4 - 64bit mmio support */ u8 rsvd13[11]; /* 0xf5 - rsvd */ -} __attribute__((packed)) global_nvs_t; +} __packed global_nvs_t; void acpi_create_gnvs(global_nvs_t *gnvs); #ifdef __SMM__ diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c index 39d67c52d5..db84914070 100644 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ b/src/southbridge/intel/fsp_rangeley/spi.c @@ -17,6 +17,7 @@ #include <stdint.h> #include <stdlib.h> #include <string.h> +#include <compiler.h> #include <commonlib/helpers.h> #include <delay.h> #include <arch/io.h> @@ -73,7 +74,7 @@ typedef struct ich7_spi_regs { uint16_t preop; uint16_t optype; uint8_t opmenu[8]; -} __attribute__((packed)) ich7_spi_regs; +} __packed ich7_spi_regs; typedef struct ich9_spi_regs { uint32_t bfpr; // 0 @@ -106,7 +107,7 @@ typedef struct ich9_spi_regs { uint32_t srdl; uint32_t srdc; uint32_t srd; -} __attribute__((packed)) ich9_spi_regs; +} __packed ich9_spi_regs; typedef struct ich10_spi_regs { uint32_t bfpr; @@ -138,7 +139,7 @@ typedef struct ich10_spi_regs { uint32_t scs; uint32_t bcr; uint32_t tcgc; -} __attribute__((packed)) ich10_spi_regs; +} __packed ich10_spi_regs; typedef struct ich_spi_controller { int locked; diff --git a/src/southbridge/intel/i82801dx/nvs.h b/src/southbridge/intel/i82801dx/nvs.h index 9db504f840..bdc6b45a56 100644 --- a/src/southbridge/intel/i82801dx/nvs.h +++ b/src/southbridge/intel/i82801dx/nvs.h @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include <compiler.h> + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ @@ -130,4 +132,4 @@ typedef struct { u8 dock; /* 0xf0 - Docking Status */ u8 bten; u8 rsvd13[14]; -} __attribute__((packed)) global_nvs_t; +} __packed global_nvs_t; diff --git a/src/southbridge/intel/i82801gx/nvs.h b/src/southbridge/intel/i82801gx/nvs.h index 49c6fc1db5..c3a3920596 100644 --- a/src/southbridge/intel/i82801gx/nvs.h +++ b/src/southbridge/intel/i82801gx/nvs.h @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include <compiler.h> + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ @@ -130,6 +132,6 @@ typedef struct { u8 dock; /* 0xf0 - Docking Status */ u8 bten; u8 rsvd13[14]; -} __attribute__((packed)) global_nvs_t; +} __packed global_nvs_t; void acpi_create_gnvs(global_nvs_t *gnvs); diff --git a/src/southbridge/intel/i82801ix/nvs.h b/src/southbridge/intel/i82801ix/nvs.h index 49c6fc1db5..c3a3920596 100644 --- a/src/southbridge/intel/i82801ix/nvs.h +++ b/src/southbridge/intel/i82801ix/nvs.h @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include <compiler.h> + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ @@ -130,6 +132,6 @@ typedef struct { u8 dock; /* 0xf0 - Docking Status */ u8 bten; u8 rsvd13[14]; -} __attribute__((packed)) global_nvs_t; +} __packed global_nvs_t; void acpi_create_gnvs(global_nvs_t *gnvs); diff --git a/src/southbridge/intel/ibexpeak/me.h b/src/southbridge/intel/ibexpeak/me.h index 06495c1963..d62b22ad5e 100644 --- a/src/southbridge/intel/ibexpeak/me.h +++ b/src/southbridge/intel/ibexpeak/me.h @@ -17,6 +17,8 @@ #ifndef _INTEL_ME_H #define _INTEL_ME_H +#include <compiler.h> + #define ME_RETRY 100000 /* 1 second */ #define ME_DELAY 10 /* 10 us */ @@ -75,7 +77,7 @@ struct me_hfs { u32 boot_options_present: 1; u32 ack_data: 3; u32 bios_msg_ack: 4; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_UMA 0x44 @@ -85,7 +87,7 @@ struct me_uma { u32 valid: 1; u32 reserved_0: 14; u32 set_to_one: 1; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_H_GS 0x4c #define ME_INIT_DONE 1 @@ -98,7 +100,7 @@ struct me_did { u32 reserved: 8; u32 status: 4; u32 init_done: 4; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_GMES 0x48 #define ME_GMES_PHASE_ROM 0 @@ -124,7 +126,7 @@ struct me_gmes { u32 current_state: 8; u32 current_pmevent: 4; u32 progress_code: 4; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_HERES 0xbc #define PCI_ME_EXT_SHA1 0x00 @@ -136,7 +138,7 @@ struct me_heres { u32 reserved: 26; u32 extend_feature_present: 1; u32 extend_reg_valid: 1; -} __attribute__ ((packed)); +} __packed; /* * Management Engine MEI registers @@ -157,7 +159,7 @@ struct mei_csr { u32 buffer_read_ptr: 8; u32 buffer_write_ptr: 8; u32 buffer_depth: 8; -} __attribute__ ((packed)); +} __packed; #define MEI_ADDRESS_CORE 0x01 #define MEI_ADDRESS_AMT 0x02 @@ -175,7 +177,7 @@ struct mei_header { u32 length: 9; u32 reserved: 6; u32 is_complete: 1; -} __attribute__ ((packed)); +} __packed; #define MKHI_GROUP_ID_CBM 0x00 #define MKHI_GROUP_ID_FWCAPS 0x03 @@ -199,7 +201,7 @@ struct mkhi_header { u32 is_response: 1; u32 reserved: 8; u32 result: 8; -} __attribute__ ((packed)); +} __packed; struct me_fw_version { u16 code_minor; @@ -210,7 +212,7 @@ struct me_fw_version { u16 recovery_major; u16 recovery_build_number; u16 recovery_hot_fix; -} __attribute__ ((packed)); +} __packed; #define HECI_EOP_STATUS_SUCCESS 0x0 @@ -225,7 +227,7 @@ struct me_fw_version { struct me_global_reset { u8 request_origin; u8 reset_type; -} __attribute__ ((packed)); +} __packed; typedef enum { ME_NORMAL_BIOS_PATH, @@ -255,7 +257,7 @@ typedef struct { u32 minor_version : 16; u32 hotfix_version : 16; u32 build_version : 16; -} __attribute__ ((packed)) mbp_fw_version_name; +} __packed mbp_fw_version_name; typedef struct { u8 num_icc_profiles; @@ -263,7 +265,7 @@ typedef struct { u8 icc_profile_index; u8 reserved; u32 register_lock_mask[3]; -} __attribute__ ((packed)) mbp_icc_profile; +} __packed mbp_icc_profile; typedef struct { u32 full_net : 1; @@ -286,7 +288,7 @@ typedef struct { u32 reserved_4 : 1; u32 wlan : 1; u32 reserved_5 : 8; -} __attribute__ ((packed)) mefwcaps_sku; +} __packed mefwcaps_sku; typedef struct { u16 lock_state : 1; @@ -297,13 +299,13 @@ typedef struct { u16 wwan3gpresent : 1; u16 wwan3goob : 1; u16 reserved : 9; -} __attribute__ ((packed)) tdt_state_flag; +} __packed tdt_state_flag; typedef struct { u8 state; u8 last_theft_trigger; tdt_state_flag flags; -} __attribute__ ((packed)) tdt_state_info; +} __packed tdt_state_info; typedef struct { u32 platform_target_usage_type : 4; @@ -313,7 +315,7 @@ typedef struct { u32 intel_me_fw_image_type : 4; u32 platform_brand : 4; u32 reserved_1 : 16; -} __attribute__ ((packed)) platform_type_rule_data; +} __packed platform_type_rule_data; typedef struct { mefwcaps_sku fw_capabilities; @@ -324,7 +326,7 @@ typedef struct { u16 device_id; u16 fuse_test_flags; u32 umchid[4]; -} __attribute__ ((packed)) mbp_rom_bist_data; +} __packed mbp_rom_bist_data; typedef struct { u32 key[8]; @@ -350,20 +352,20 @@ typedef struct { u32 mbp_size : 8; u32 num_entries : 8; u32 rsvd : 16; -} __attribute__ ((packed)) mbp_header; +} __packed mbp_header; typedef struct { u32 app_id : 8; u32 item_id : 8; u32 length : 8; u32 rsvd : 8; -} __attribute__ ((packed)) mbp_item_header; +} __packed mbp_item_header; struct me_fwcaps { u32 id; u8 length; mefwcaps_sku caps_sku; u8 reserved[3]; -} __attribute__ ((packed)); +} __packed; #endif /* _INTEL_ME_H */ diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h index 1c0011a823..6cd8ec3c4f 100644 --- a/src/southbridge/intel/ibexpeak/nvs.h +++ b/src/southbridge/intel/ibexpeak/nvs.h @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <compiler.h> #include "vendorcode/google/chromeos/gnvs.h" typedef struct { /* Miscellaneous */ @@ -148,7 +149,7 @@ typedef struct { /* ChromeOS specific (starts at 0x100)*/ chromeos_acpi_t chromeos; -} __attribute__((packed)) global_nvs_t; +} __packed global_nvs_t; #ifdef __SMM__ /* Used in SMM to find the ACPI GNVS address */ diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h index 64e9c31931..6c21db228e 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.h +++ b/src/southbridge/intel/lynxpoint/lp_gpio.h @@ -16,6 +16,8 @@ #ifndef INTEL_LYNXPOINT_LP_GPIO_H #define INTEL_LYNXPOINT_LP_GPIO_H +#include <compiler.h> + /* LynxPoint LP GPIOBASE Registers */ #define GPIO_OWNER(set) (0x00 + ((set) * 4)) #define GPIO_PIRQ_APIC_EN 0x10 @@ -158,7 +160,7 @@ struct pch_lp_gpio_map { u8 reset; u8 blink; u8 pirq; -} __attribute__ ((packed)); +} __packed; /* Configure GPIOs with mainboard provided settings */ void setup_pch_lp_gpios(const struct pch_lp_gpio_map map[]); diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h index 912fb62e37..a1987eb55e 100644 --- a/src/southbridge/intel/lynxpoint/me.h +++ b/src/southbridge/intel/lynxpoint/me.h @@ -17,6 +17,8 @@ #ifndef _INTEL_ME_H #define _INTEL_ME_H +#include <compiler.h> + #define ME_RETRY 100000 /* 1 second */ #define ME_DELAY 10 /* 10 us */ @@ -75,7 +77,7 @@ struct me_hfs { u32 boot_options_present: 1; u32 ack_data: 3; u32 bios_msg_ack: 4; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_UMA 0x44 @@ -85,7 +87,7 @@ struct me_uma { u32 valid: 1; u32 reserved_0: 14; u32 set_to_one: 1; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_H_GS 0x4c #define ME_INIT_DONE 1 @@ -100,7 +102,7 @@ struct me_did { u32 rapid_start: 1; u32 status: 4; u32 init_done: 4; -} __attribute__ ((packed)); +} __packed; /* * Apparently the GMES register is renamed to HFS2 (or HFSTS2 according @@ -191,7 +193,7 @@ struct me_hfs2 { u32 current_state: 8; u32 current_pmevent: 4; u32 progress_code: 4; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_H_GS2 0x70 #define PCI_ME_MBP_GIVE_UP 0x01 @@ -206,7 +208,7 @@ struct me_heres { u32 reserved: 26; u32 extend_feature_present: 1; u32 extend_reg_valid: 1; -} __attribute__ ((packed)); +} __packed; /* * Management Engine MEI registers @@ -227,7 +229,7 @@ struct mei_csr { u32 buffer_read_ptr: 8; u32 buffer_write_ptr: 8; u32 buffer_depth: 8; -} __attribute__ ((packed)); +} __packed; #define MEI_ADDRESS_CORE 0x01 #define MEI_ADDRESS_AMT 0x02 @@ -245,7 +247,7 @@ struct mei_header { u32 length: 9; u32 reserved: 6; u32 is_complete: 1; -} __attribute__ ((packed)); +} __packed; #define MKHI_GROUP_ID_CBM 0x00 #define MKHI_GROUP_ID_FWCAPS 0x03 @@ -268,7 +270,7 @@ struct mkhi_header { u32 is_response: 1; u32 reserved: 8; u32 result: 8; -} __attribute__ ((packed)); +} __packed; struct me_fw_version { u16 code_minor; @@ -279,7 +281,7 @@ struct me_fw_version { u16 recovery_major; u16 recovery_build_number; u16 recovery_hot_fix; -} __attribute__ ((packed)); +} __packed; /* ICC Messages */ #define ICC_SET_CLOCK_ENABLES 0x3 @@ -291,14 +293,14 @@ struct icc_header { u32 icc_status; u32 length; u32 reserved; -} __attribute__ ((packed)); +} __packed; struct icc_clock_enables_msg { u32 clock_enables; u32 clock_mask; u32 no_response: 1; u32 reserved: 31; -} __attribute__ ((packed)); +} __packed; #define HECI_EOP_STATUS_SUCCESS 0x0 #define HECI_EOP_PERFORM_GLOBAL_RESET 0x1 @@ -312,7 +314,7 @@ struct icc_clock_enables_msg { struct me_global_reset { u8 request_origin; u8 reset_type; -} __attribute__ ((packed)); +} __packed; typedef enum { ME_NORMAL_BIOS_PATH, @@ -373,21 +375,21 @@ typedef struct { u32 mbp_size : 8; u32 num_entries : 8; u32 rsvd : 16; -} __attribute__ ((packed)) mbp_header; +} __packed mbp_header; typedef struct { u32 app_id : 8; u32 item_id : 8; u32 length : 8; u32 rsvd : 8; -} __attribute__ ((packed)) mbp_item_header; +} __packed mbp_item_header; typedef struct { u32 major_version : 16; u32 minor_version : 16; u32 hotfix_version : 16; u32 build_version : 16; -} __attribute__ ((packed)) mbp_fw_version_name; +} __packed mbp_fw_version_name; typedef struct { u32 full_net : 1; @@ -409,13 +411,13 @@ typedef struct { u32 reserved_4 : 1; u32 wlan : 1; u32 reserved_5 : 8; -} __attribute__ ((packed)) mbp_mefwcaps; +} __packed mbp_mefwcaps; typedef struct { u16 device_id; u16 fuse_test_flags; u32 umchid[4]; -} __attribute__ ((packed)) mbp_rom_bist_data; +} __packed mbp_rom_bist_data; typedef struct { u32 key[8]; @@ -433,7 +435,7 @@ typedef struct { u32 image_type: 4; u32 brand: 4; u32 rsvd1: 16; -} __attribute__ ((packed)) mbp_me_firmware_type; +} __packed mbp_me_firmware_type; typedef struct { mbp_me_firmware_type rule_data; @@ -443,7 +445,7 @@ typedef struct { typedef struct { u16 icc_start_address; u16 mask; -} __attribute__ ((packed)) icc_address_mask; +} __packed icc_address_mask; typedef struct { u8 num_icc_profiles; @@ -452,7 +454,7 @@ typedef struct { u8 reserved; u32 icc_reg_bundles; icc_address_mask icc_address_mask[0]; -} __attribute__ ((packed)) mbp_icc_profile; +} __packed mbp_icc_profile; typedef struct { u16 lock_state : 1; @@ -461,24 +463,24 @@ typedef struct { u16 flash_wear_out : 1; u16 flash_variable_security : 1; u16 reserved : 11; -} __attribute__ ((packed)) tdt_state_flag; +} __packed tdt_state_flag; typedef struct { u8 state; u8 last_theft_trigger; tdt_state_flag flags; -} __attribute__ ((packed)) mbp_at_state; +} __packed mbp_at_state; typedef struct { u32 wake_event_mrst_time_ms; u32 mrst_pltrst_time_ms; u32 pltrst_cpurst_time_ms; -} __attribute__ ((packed)) mbp_plat_time; +} __packed mbp_plat_time; typedef struct { u32 device_type : 2; u32 reserved : 30; -} __attribute__ ((packed)) mbp_nfc_data; +} __packed mbp_nfc_data; typedef struct { mbp_fw_version_name *fw_version_name; @@ -498,6 +500,6 @@ struct me_fwcaps { u8 length; mbp_mefwcaps caps_sku; u8 reserved[3]; -} __attribute__ ((packed)); +} __packed; #endif /* _INTEL_ME_H */ diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h index 50936cf5e1..667a6dba1b 100644 --- a/src/southbridge/intel/lynxpoint/nvs.h +++ b/src/southbridge/intel/lynxpoint/nvs.h @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <compiler.h> #include "vendorcode/google/chromeos/gnvs.h" typedef struct { /* Miscellaneous */ @@ -124,7 +125,7 @@ typedef struct { /* ChromeOS specific (starts at 0x100)*/ chromeos_acpi_t chromeos; -} __attribute__((packed)) global_nvs_t; +} __packed global_nvs_t; #ifdef __SMM__ /* Used in SMM to find the ACPI GNVS address */ diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.h b/src/southbridge/ricoh/rl5c476/rl5c476.h index 7ab5faf961..0639fd1193 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.h +++ b/src/southbridge/ricoh/rl5c476/rl5c476.h @@ -17,6 +17,7 @@ /* rl5c476 routines and defines*/ +#include <compiler.h> #include <stdint.h> @@ -87,4 +88,4 @@ typedef struct pc16reg { u8 resv8; u8 resv9; u8 smpga0; -} __attribute__ ((packed)) pc16reg_t; +} __packed pc16reg_t; diff --git a/src/southbridge/via/vt8237r/nvs.h b/src/southbridge/via/vt8237r/nvs.h index 9e543d4222..894bfe89fa 100644 --- a/src/southbridge/via/vt8237r/nvs.h +++ b/src/southbridge/via/vt8237r/nvs.h @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include <compiler.h> + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ @@ -38,4 +40,4 @@ typedef struct { u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ u8 ppcm; /* 0x2c - Max. PPC state */ -} __attribute__((packed)) global_nvs_t; +} __packed global_nvs_t; diff --git a/src/southbridge/via/vt8237r/vt8237r.h b/src/southbridge/via/vt8237r/vt8237r.h index 95f9750a40..e195a299d9 100644 --- a/src/southbridge/via/vt8237r/vt8237r.h +++ b/src/southbridge/via/vt8237r/vt8237r.h @@ -16,6 +16,8 @@ #ifndef SOUTHBRIDGE_VIA_VT8237R_VT8237R_H #define SOUTHBRIDGE_VIA_VT8237R_VT8237R_H +#include <compiler.h> + /* Static resources for the VT8237R southbridge */ #define VT8237R_APIC_ID 0x2 @@ -121,7 +123,7 @@ struct vt8237_network_rom { u8 cfg_c; u8 cfg_d; u8 checksum; -} __attribute__ ((packed)); +} __packed; #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 diff --git a/src/vboot/vboot_common.h b/src/vboot/vboot_common.h index 8421ecb640..8c92f7f131 100644 --- a/src/vboot/vboot_common.h +++ b/src/vboot/vboot_common.h @@ -17,6 +17,7 @@ #include <commonlib/region.h> #include <stdint.h> +#include <compiler.h> #include <vboot_api.h> #include <vboot_struct.h> @@ -42,7 +43,7 @@ struct vboot_handoff { VbInitParams init_params; uint32_t selected_firmware; char shared_data[VB_SHARED_DATA_MIN_SIZE]; -} __attribute__((packed)); +} __packed; /* * vboot_get_handoff_info returns pointer to the vboot_handoff structure if diff --git a/src/vendorcode/amd/include/Porting.h b/src/vendorcode/amd/include/Porting.h index ee0f074d3a..ed1a9c707e 100644 --- a/src/vendorcode/amd/include/Porting.h +++ b/src/vendorcode/amd/include/Porting.h @@ -243,11 +243,11 @@ #define CONST const #define ROMDATA #define CALLCONV - #define _16BYTE_ALIGN __attribute__ ((aligned (16))) - #define _8BYTE_ALIGN __attribute__ ((aligned (8))) - #define _4BYTE_ALIGN __attribute__ ((aligned (4))) - #define _2BYTE_ALIGN __attribute__ ((aligned (2))) - #define _1BYTE_ALIGN __attribute__ ((aligned (1))) + #define _16BYTE_ALIGN __attribute__((aligned (16))) + #define _8BYTE_ALIGN __attribute__((aligned (8))) + #define _4BYTE_ALIGN __attribute__((aligned (4))) + #define _2BYTE_ALIGN __attribute__((aligned (2))) + #define _1BYTE_ALIGN __attribute__((aligned (1))) typedef uintptr_t UINTN; typedef int64_t INT64; diff --git a/src/vendorcode/amd/include/gcc-intrin.h b/src/vendorcode/amd/include/gcc-intrin.h index 8b31530a8a..44e91d28b6 100644 --- a/src/vendorcode/amd/include/gcc-intrin.h +++ b/src/vendorcode/amd/include/gcc-intrin.h @@ -581,8 +581,8 @@ __readfsdword(unsigned long Offset) } #ifdef __SSE3__ -typedef long long __v2di __attribute__ ((__vector_size__ (16))); -typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__)); +typedef long long __v2di __attribute__((__vector_size__ (16))); +typedef long long __m128i __attribute__((__vector_size__ (16), __may_alias__)); static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs2 (void *__A, __m128i __B) { diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h index 10f738636f..82cd409e8e 100644 --- a/src/vendorcode/google/chromeos/gnvs.h +++ b/src/vendorcode/google/chromeos/gnvs.h @@ -16,6 +16,8 @@ #ifndef __VENDORCODE_GOOGLE_CHROMEOS_GNVS_H #define __VENDORCODE_GOOGLE_CHROMEOS_GNVS_H +#include <compiler.h> + #define BOOT_REASON_OTHER 0 #define BOOT_REASON_S3DIAG 9 @@ -57,7 +59,7 @@ typedef struct { u32 ramoops_base; // dbe ramoops base address u32 ramoops_len; // dc2 ramoops length u8 pad[314]; // dc6-eff -} __attribute__((packed)) chromeos_acpi_t; +} __packed chromeos_acpi_t; extern chromeos_acpi_t *vboot_data; void chromeos_init_vboot(chromeos_acpi_t *chromeos); diff --git a/src/vendorcode/google/chromeos/vpd_tables.h b/src/vendorcode/google/chromeos/vpd_tables.h index d58b5e846d..822ed08b0f 100644 --- a/src/vendorcode/google/chromeos/vpd_tables.h +++ b/src/vendorcode/google/chromeos/vpd_tables.h @@ -9,6 +9,7 @@ #ifndef __LIB_VPD_TABLES_H__ #define __LIB_VPD_TABLES_H__ +#include <compiler.h> #include <inttypes.h> #define VPD_ENTRY_MAGIC "_SM_" @@ -32,7 +33,7 @@ struct google_vpd_info { uint8_t magic[12]; } header; uint32_t size; -} __attribute__((packed)); +} __packed; /* Entry */ struct vpd_entry { @@ -50,14 +51,14 @@ struct vpd_entry { uint32_t table_address; uint16_t table_entry_count; uint8_t bcd_revision; -} __attribute__ ((packed)); +} __packed; /* Header */ struct vpd_header { uint8_t type; uint8_t length; uint16_t handle; -} __attribute__ ((packed)); +} __packed; /* Type 0 - firmware information */ struct vpd_table_firmware { @@ -72,7 +73,7 @@ struct vpd_table_firmware { uint8_t minor_ver; /* v2.4+ */ uint8_t ec_major_ver; /* v2.4+ */ uint8_t ec_minor_ver; /* v2.4+ */ -} __attribute__ ((packed)); +} __packed; /* Type 1 - system information */ struct vpd_table_system { @@ -84,12 +85,12 @@ struct vpd_table_system { uint8_t wakeup_type; uint8_t sku_number; /* v2.4+ */ uint8_t family; /* v2.4+ */ -} __attribute__ ((packed)); +} __packed; /* Type 127 - end of table */ struct vpd_table_eot { struct vpd_header header; -} __attribute__ ((packed)); +} __packed; /* Type 241 - binary blob pointer */ struct vpd_table_binary_blob_pointer { @@ -104,7 +105,7 @@ struct vpd_table_binary_blob_pointer { uint8_t uuid[16]; uint32_t offset; uint32_t size; -} __attribute__ ((packed)); +} __packed; /* The length and number of strings defined here is not a limitation of VPD. * These numbers were deemed good enough during development. */ |