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| author | Tim Chen <tim-chen@quanta.corp-partner.google.com> | 2020-01-17 15:00:00 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-01-18 11:20:19 +0000 |
| commit | 6ce42616bb8524ff6033f6d6439426ca07bfd45a (patch) | |
| tree | 51020a81e69828ea80460dc13e39ca3ddd9de83a /src | |
| parent | c004857da06dd90be9a1ac34bd6efe2bc03fed6a (diff) | |
| download | coreboot-6ce42616bb8524ff6033f6d6439426ca07bfd45a.tar.xz | |
mainboard/google/puff: update SATA strength
Base on SATA SI report to fine tune the strength for port 1.
BRANCH=none
BUG=b:147351936
TEST=build and test SATA port works fine.
Change-Id: Ib82b7e5df32b4ce794682781f33c44dfeb6e68bf
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/hatch/variants/puff/overridetree.cb | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index 402b98bc9a..2e40ba9fc1 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -171,6 +171,11 @@ chip soc/intel/cannonlake # GPIO for SD card detect register "sdcard_cd_gpio" = "vSD3_CD_B" + # SATA port 1 Gen3 Strength + # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB + register "sata_port[1].TxGen3DeEmphEnable" = "1" + register "sata_port[1].TxGen3DeEmph" = "0x20" + device domain 0 on device pci 14.0 on chip drivers/usb/acpi |