diff options
| author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2015-01-04 21:33:39 +1100 |
|---|---|---|
| committer | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2015-01-06 01:51:42 +0100 |
| commit | 77757c22b9eede92234d07d65a23fdf4b970c8cf (patch) | |
| tree | 29949ed8cfac9c5c9b2cf4c8071c74690411d32d /src | |
| parent | d76ac6349df0147b9d8f7f09f8bb80343ecfb5e6 (diff) | |
| download | coreboot-77757c22b9eede92234d07d65a23fdf4b970c8cf.tar.xz | |
mainboard/*/romstage.c: Sanitize system header inclusions
Fix system include paths to be consistent. Chipset support is
part of the Coreboot 'system' and hence 'non-local' (i.e., in
the same directory or context). One possible product of this, is
to perhaps allow future work to do pre-compiled headers (PCH) on
the buildbot for faster build times. However, this currently just
makes mainboard's consistent.
Change-Id: I2f3fd8a3d7864926461c960ca619bff635d7dea5
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8085
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src')
181 files changed, 682 insertions, 682 deletions
diff --git a/src/mainboard/a-trend/atc-6220/romstage.c b/src/mainboard/a-trend/atc-6220/romstage.c index 16c9286e89..155a86d390 100644 --- a/src/mainboard/a-trend/atc-6220/romstage.c +++ b/src/mainboard/a-trend/atc-6220/romstage.c @@ -24,11 +24,11 @@ #include <device/pnp_def.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/a-trend/atc-6240/romstage.c b/src/mainboard/a-trend/atc-6240/romstage.c index 8485285abd..baf8972e57 100644 --- a/src/mainboard/a-trend/atc-6240/romstage.c +++ b/src/mainboard/a-trend/atc-6240/romstage.c @@ -24,11 +24,11 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <lib.h> diff --git a/src/mainboard/aaeon/pfm-540i_revb/romstage.c b/src/mainboard/aaeon/pfm-540i_revb/romstage.c index a664e9e06f..7c44614212 100644 --- a/src/mainboard/aaeon/pfm-540i_revb/romstage.c +++ b/src/mainboard/aaeon/pfm-540i_revb/romstage.c @@ -27,15 +27,15 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" #include <superio/smsc/smscsuperio/smscsuperio.h> -#include "northbridge/amd/lx/raminit.h" +#include <northbridge/amd/lx/raminit.h> #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) diff --git a/src/mainboard/abit/be6-ii_v2_0/romstage.c b/src/mainboard/abit/be6-ii_v2_0/romstage.c index 63dfec6f97..9f918bbb31 100644 --- a/src/mainboard/abit/be6-ii_v2_0/romstage.c +++ b/src/mainboard/abit/be6-ii_v2_0/romstage.c @@ -24,11 +24,11 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> /* FIXME: It's a Winbond W83977EF, actually. */ #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index 1167bf5560..ecd507595c 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -35,12 +35,12 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" -#include "cpu/x86/lapic.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/amd/mtrr.h> @@ -66,7 +66,7 @@ static int spd_read_byte(u32 device, u32 address) #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" #include "spd.h" diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index ef85df2bed..73c41e3dda 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -34,13 +34,13 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" @@ -57,12 +57,12 @@ static int spd_read_byte(u32 device, u32 address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c index 63e9275141..e7532cf540 100644 --- a/src/mainboard/amd/db800/romstage.c +++ b/src/mainboard/amd/db800/romstage.c @@ -24,16 +24,16 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "northbridge/amd/lx/raminit.h" +#include <northbridge/amd/lx/raminit.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index c9a04f5eef..5b9b6ca0ad 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -26,14 +26,14 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include <spd.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" @@ -49,7 +49,7 @@ static inline int spd_read_byte(u32 device, u32 address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index ad6bce358d..64efdd642d 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -30,10 +30,10 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/smsc/sch4037/sch4037.h> #include <superio/smsc/sio1036/sio1036.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "nb_cimx.h" #include <sb_cimx.h> diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index 1a80e5ce13..1f63979263 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -32,9 +32,9 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/smsc/kbc1100/kbc1100.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include <sb_cimx.h> #include "SBPLATFORM.h" diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index 00223aed74..6e3de074fc 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -27,17 +27,17 @@ #include <console/console.h> #include <spd.h> #include <cpu/amd/model_fxx_rev.h> -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/smbus.h> #include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */ #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) @@ -50,7 +50,7 @@ static inline int spd_read_byte(u32 device, u32 address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index b940be0964..0a6a3308f7 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -34,20 +34,20 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/smbus.h> #include "northbridge/amd/amdfam10/debug.c" #include <spd.h> @@ -60,12 +60,12 @@ static int spd_read_byte(u32 device, u32 address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c index 2c8293742f..9daa1d6776 100644 --- a/src/mainboard/amd/norwich/romstage.c +++ b/src/mainboard/amd/norwich/romstage.c @@ -24,14 +24,14 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "northbridge/amd/lx/raminit.h" +#include <northbridge/amd/lx/raminit.h> int spd_read_byte(unsigned int device, unsigned int address) { diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index 82dcd602de..226278236f 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -31,10 +31,10 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" -#include "southbridge/amd/agesa/hudson/hudson.h" -#include "cpu/amd/agesa/s3_resume.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <southbridge/amd/agesa/hudson/hudson.h> +#include <cpu/amd/agesa/s3_resume.h> #include "cbmem.h" diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c index f603d738c5..6fa3af6bb9 100644 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ b/src/mainboard/amd/olivehillplus/romstage.c @@ -32,10 +32,10 @@ #include <cpu/amd/car.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" -#include "southbridge/amd/pi/avalon/hudson.h" -#include "cpu/amd/pi/s3_resume.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <southbridge/amd/pi/avalon/hudson.h> +#include <cpu/amd/pi/s3_resume.h> void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index e38d715c8b..1fb709a372 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -31,10 +31,10 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" -#include "southbridge/amd/agesa/hudson/hudson.h" -#include "cpu/amd/agesa/s3_resume.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <southbridge/amd/agesa/hudson/hudson.h> +#include <cpu/amd/agesa/s3_resume.h> #include "cbmem.h" diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 581c2c2858..2fdab4153c 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -32,16 +32,16 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include <cpu/x86/cache.h> #include <sb_cimx.h> #include "SBPLATFORM.h" #include "cbmem.h" -#include "cpu/amd/mtrr.h" -#include "cpu/amd/agesa/s3_resume.h" +#include <cpu/amd/mtrr.h> +#include <cpu/amd/agesa/s3_resume.h> #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index af4253d705..906ff850cf 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -26,12 +26,12 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <spd.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" @@ -45,7 +45,7 @@ static inline int spd_read_byte(u32 device, u32 address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c index 248baa0d3a..fb21b2f3c6 100644 --- a/src/mainboard/amd/rumba/romstage.c +++ b/src/mainboard/amd/rumba/romstage.c @@ -5,8 +5,8 @@ #include <console/console.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/gx2def.h> #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" @@ -22,7 +22,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/gx2/raminit.h" +#include <northbridge/amd/gx2/raminit.h> #include "northbridge/amd/gx2/pll_reset.c" #include "northbridge/amd/gx2/raminit.c" #include "lib/generic_sdram.c" diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index ec0682a667..f49aa61dd1 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -9,9 +9,9 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/amd/amd8111/early_smbus.c" #include <reset.h> -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "northbridge/amd/amdk8/reset_test.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/debug.c" #include <cpu/amd/mtrr.h> @@ -50,7 +50,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index df968c3e96..749b48ede6 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -35,14 +35,14 @@ #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> #include "southbridge/amd/amd8111/early_smbus.c" -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> #include <spd.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdfam10/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> @@ -79,12 +79,12 @@ static int spd_read_byte(u32 device, u32 address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index ccf84b61cf..5f902c312e 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -32,10 +32,10 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include <sb_cimx.h> #include "SBPLATFORM.h" diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 319cd3a8bd..30808a4dfd 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -31,11 +31,11 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" -#include "southbridge/amd/agesa/hudson/hudson.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <southbridge/amd/agesa/hudson/hudson.h> #include "src/superio/smsc/lpc47n217/early_serial.c" -#include "cpu/amd/agesa/s3_resume.h" +#include <cpu/amd/agesa/s3_resume.h> #include "cbmem.h" #define SERIAL_DEV PNP_DEV(0x2e, LPC47N217_SP1) diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index c4ccc70096..0b6b7db594 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -34,20 +34,20 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/smbus.h> #include "northbridge/amd/amdfam10/debug.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) @@ -59,12 +59,12 @@ static int spd_read_byte(u32 device, u32 address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index e3f41a070b..6c2f2c5b16 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -29,9 +29,9 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/smsc/kbc1100/kbc1100.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "sb_cimx.h" #include "SbPlatform.h" #include <arch/cpu.h> diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index c75cf7a270..714eb3c1fe 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -32,8 +32,8 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> #include <sb_cimx.h> #include "SBPLATFORM.h" diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index 8bb179aee5..b42ff2e418 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -25,8 +25,8 @@ #include <console/console.h> #include <cpu/x86/bist.h> -#include "southbridge/intel/i82801dx/i82801dx.h" -#include "northbridge/intel/e7505/raminit.h" +#include <southbridge/intel/i82801dx/i82801dx.h> +#include <northbridge/intel/e7505/raminit.h> #include <device/pnp_def.h> #include <superio/smsc/lpc47m10x/lpc47m10x.h> diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 443fdc55af..dfa6847a31 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -36,9 +36,9 @@ #include <console/console.h> #include <cpu/x86/bist.h> #include <halt.h> -#include "northbridge/intel/i945/i945.h" -#include "northbridge/intel/i945/raminit.h" -#include "southbridge/intel/i82801gx/i82801gx.h" +#include <northbridge/intel/i945/i945.h> +#include <northbridge/intel/i945/raminit.h> +#include <southbridge/intel/i82801gx/i82801gx.h> void setup_ich7_gpios(void) { diff --git a/src/mainboard/arima/hdama/romstage.c b/src/mainboard/arima/hdama/romstage.c index 137d3ebede..c360245d55 100644 --- a/src/mainboard/arima/hdama/romstage.c +++ b/src/mainboard/arima/hdama/romstage.c @@ -8,12 +8,12 @@ #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/nsc/pc87360/pc87360.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> #include "southbridge/amd/amd8111/early_ctrl.c" diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c index 63f89f1d6c..7d753b302e 100644 --- a/src/mainboard/artecgroup/dbe61/romstage.c +++ b/src/mainboard/artecgroup/dbe61/romstage.c @@ -24,15 +24,15 @@ #include <device/pnp_def.h> #include <stdlib.h> #include <console/console.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include "spd_table.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "northbridge/amd/lx/raminit.h" +#include <northbridge/amd/lx/raminit.h> int spd_read_byte(unsigned int device, unsigned int address) { diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index 417f9a7845..16cc02b213 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -27,18 +27,18 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include <spd.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/smbus.h> #include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */ #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) @@ -52,7 +52,7 @@ static inline int spd_read_byte(u32 device, u32 address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 604c923fc2..aabdd74918 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -31,10 +31,10 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct5572d/nct5572d.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include <sb_cimx.h> #include "SBPLATFORM.h" diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 1ba1104eb0..efeed35005 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -31,10 +31,10 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" -#include "southbridge/amd/agesa/hudson/hudson.h" -#include "cpu/amd/agesa/s3_resume.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <southbridge/amd/agesa/hudson/hudson.h> +#include <cpu/amd/agesa/s3_resume.h> #include "cbmem.h" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627uhg/w83627uhg.h> diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c index c0fa6a52fd..34f4514d0b 100644 --- a/src/mainboard/asus/a8n_e/romstage.c +++ b/src/mainboard/asus/a8n_e/romstage.c @@ -32,18 +32,18 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include <cpu/amd/model_fxx_rev.h> #include <console/console.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/nvidia/ck804/early_smbus.h" -#include "northbridge/amd/amdk8/raminit.h" +#include <southbridge/nvidia/ck804/early_smbus.h> +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/debug.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "cpu/amd/dualcore/dualcore.c" @@ -59,7 +59,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit.c" #include "lib/generic_sdram.c" -#include "southbridge/nvidia/ck804/early_setup_ss.h" +#include <southbridge/nvidia/ck804/early_setup_ss.h> #include "southbridge/nvidia/ck804/early_setup.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index 0d55e532f0..f96d4be5e5 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -34,16 +34,16 @@ unsigned int get_sbdn(unsigned bus); #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include <halt.h> -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include "southbridge/via/vt8237r/early_smbus.c" #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> @@ -76,7 +76,7 @@ void soft_reset(void) } #include "southbridge/via/k8t890/early_car.c" -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 3ed2491737..0b954750b5 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -34,16 +34,16 @@ unsigned int get_sbdn(unsigned bus); #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include <halt.h> -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include "southbridge/via/vt8237r/early_smbus.c" #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> @@ -76,7 +76,7 @@ void soft_reset(void) } #include "southbridge/via/k8t890/early_car.c" -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" diff --git a/src/mainboard/asus/dsbf/romstage.c b/src/mainboard/asus/dsbf/romstage.c index fbd0848f9b..d7bcb89554 100644 --- a/src/mainboard/asus/dsbf/romstage.c +++ b/src/mainboard/asus/dsbf/romstage.c @@ -32,8 +32,8 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <northbridge/intel/i5000/raminit.h> -#include "northbridge/intel/i3100/i3100.h" -#include "southbridge/intel/i3100/i3100.h" +#include <northbridge/intel/i3100/i3100.h> +#include <southbridge/intel/i3100/i3100.h> #include <southbridge/intel/i3100/early_smbus.c> #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0) diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index dab3193d70..2f8dc4fb4e 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -34,16 +34,16 @@ unsigned int get_sbdn(unsigned bus); #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include <halt.h> -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83697hf/w83697hf.h> #include "southbridge/via/vt8237r/early_smbus.c" #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> @@ -74,7 +74,7 @@ void soft_reset(void) } #include "southbridge/via/k8t890/early_car.c" -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index d12b77c5be..4cf64cc571 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -31,15 +31,15 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include <lib.h> #include <spd.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8716f/it8716f.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" @@ -55,14 +55,14 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/f.h" +#include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" -#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 42b03c8a7a..87d0d713f3 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -35,14 +35,14 @@ unsigned int get_sbdn(unsigned bus); #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include <halt.h> -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include "southbridge/via/vt8237r/early_smbus.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> @@ -58,7 +58,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) } #include "southbridge/via/k8t890/early_car.c" -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index f776351d14..f5c56549b6 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -35,14 +35,14 @@ unsigned int get_sbdn(unsigned bus); #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include <halt.h> -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include "southbridge/via/vt8237r/early_smbus.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> @@ -61,7 +61,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) } #include "southbridge/via/k8t890/early_car.c" -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 9da8c6c669..01df5c8cbe 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -34,20 +34,20 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/smbus.h> #include "northbridge/amd/amdfam10/debug.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) @@ -60,12 +60,12 @@ static int spd_read_byte(u32 device, u32 address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index dcf2b2215c..9b14cd355a 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -34,20 +34,20 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/smbus.h> #include "northbridge/amd/amdfam10/debug.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) @@ -60,12 +60,12 @@ static int spd_read_byte(u32 device, u32 address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index a2fcedad11..3bf8e80f36 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -35,12 +35,12 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" -#include "cpu/x86/lapic.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8721f/it8721f.h> #include <cpu/amd/mtrr.h> @@ -64,7 +64,7 @@ static int spd_read_byte(u32 device, u32 address) #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" #include "spd.h" diff --git a/src/mainboard/asus/mew-am/romstage.c b/src/mainboard/asus/mew-am/romstage.c index 15d7791ca8..213d480146 100644 --- a/src/mainboard/asus/mew-am/romstage.c +++ b/src/mainboard/asus/mew-am/romstage.c @@ -24,10 +24,10 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "southbridge/intel/i82801ax/i82801ax.h" -#include "northbridge/intel/i82810/raminit.h" +#include <southbridge/intel/i82801ax/i82801ax.h> +#include <northbridge/intel/i82810/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #include <lib.h> diff --git a/src/mainboard/asus/mew-vm/romstage.c b/src/mainboard/asus/mew-vm/romstage.c index 3c67af3fdd..f6032efd53 100644 --- a/src/mainboard/asus/mew-vm/romstage.c +++ b/src/mainboard/asus/mew-vm/romstage.c @@ -25,9 +25,9 @@ #include <stdlib.h> #include <console/console.h> #include <superio/smsc/lpc47b272/lpc47b272.h> -#include "northbridge/intel/i82810/raminit.h" -#include "cpu/x86/bist.h" -#include "southbridge/intel/i82801ax/i82801ax.h" +#include <northbridge/intel/i82810/raminit.h> +#include <cpu/x86/bist.h> +#include <southbridge/intel/i82801ax/i82801ax.h> #include "drivers/pc80/udelay_io.c" #include <lib.h> diff --git a/src/mainboard/asus/p2b-d/romstage.c b/src/mainboard/asus/p2b-d/romstage.c index 83073116ff..28e4e606a4 100644 --- a/src/mainboard/asus/p2b-d/romstage.c +++ b/src/mainboard/asus/p2b-d/romstage.c @@ -24,11 +24,11 @@ #include <device/pnp_def.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> #include <lib.h> diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c index 56992c52d0..af226d51a1 100644 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ b/src/mainboard/asus/p2b-ds/romstage.c @@ -24,11 +24,11 @@ #include <device/pnp_def.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> #include <lib.h> diff --git a/src/mainboard/asus/p2b-f/romstage.c b/src/mainboard/asus/p2b-f/romstage.c index 7cf009948f..e46ce61937 100644 --- a/src/mainboard/asus/p2b-f/romstage.c +++ b/src/mainboard/asus/p2b-f/romstage.c @@ -24,11 +24,11 @@ #include <device/pnp_def.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> /* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */ #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c index fb90a68a6a..dbc359aeab 100644 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ b/src/mainboard/asus/p2b-ls/romstage.c @@ -24,11 +24,11 @@ #include <device/pnp_def.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */ #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c index 16c9286e89..155a86d390 100644 --- a/src/mainboard/asus/p2b/romstage.c +++ b/src/mainboard/asus/p2b/romstage.c @@ -24,11 +24,11 @@ #include <device/pnp_def.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index 2655fc7a22..2636d4e19f 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -24,11 +24,11 @@ #include <device/pnp_def.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index 36ce1de6d8..2f3b0dc914 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -35,12 +35,12 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" -#include "cpu/x86/lapic.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/amd/mtrr.h> @@ -67,7 +67,7 @@ static int spd_read_byte(u32 device, u32 address) #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" #include "spd.h" diff --git a/src/mainboard/azza/pt-6ibd/romstage.c b/src/mainboard/azza/pt-6ibd/romstage.c index 804e34c793..bac20976fc 100644 --- a/src/mainboard/azza/pt-6ibd/romstage.c +++ b/src/mainboard/azza/pt-6ibd/romstage.c @@ -24,11 +24,11 @@ #include <device/pnp_def.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> /* FIXME: It's a Winbond W83977EF, actually. */ #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/bachmann/ot200/romstage.c b/src/mainboard/bachmann/ot200/romstage.c index 7951a57700..4f65cbf4f5 100644 --- a/src/mainboard/bachmann/ot200/romstage.c +++ b/src/mainboard/bachmann/ot200/romstage.c @@ -26,13 +26,13 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "northbridge/amd/lx/raminit.h" +#include <northbridge/amd/lx/raminit.h> int spd_read_byte(unsigned int device, unsigned int address) { diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c index 170a90997f..5035f576b0 100644 --- a/src/mainboard/bcom/winnetp680/romstage.c +++ b/src/mainboard/bcom/winnetp680/romstage.c @@ -25,8 +25,8 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "northbridge/via/cn700/raminit.h" -#include "cpu/x86/bist.h" +#include <northbridge/via/cn700/raminit.h> +#include <cpu/x86/bist.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include <lib.h> diff --git a/src/mainboard/biostar/m6tba/romstage.c b/src/mainboard/biostar/m6tba/romstage.c index a91318dfaf..463082086a 100644 --- a/src/mainboard/biostar/m6tba/romstage.c +++ b/src/mainboard/biostar/m6tba/romstage.c @@ -24,11 +24,11 @@ #include <device/pnp_def.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #include <lib.h> diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index a97c3b88fc..72c2dd0faa 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -9,13 +9,13 @@ #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/broadcom/bcm5785/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/nsc/pc87417/pc87417.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/broadcom/bcm5785/early_setup.c" diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c index cfda5dbeb0..ea33555de0 100644 --- a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c +++ b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c @@ -24,11 +24,11 @@ #include <device/pnp_def.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> /* FIXME: This should be PC97307 (but it's buggy at the moment)! */ #include <superio/nsc/pc97317/pc97317.h> #include <lib.h> diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c index ce8ef13a80..73fef71c44 100644 --- a/src/mainboard/digitallogic/adl855pc/romstage.c +++ b/src/mainboard/digitallogic/adl855pc/romstage.c @@ -7,12 +7,12 @@ #include "drivers/pc80/udelay_io.c" #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "southbridge/intel/i82801dx/i82801dx.h" -#include "northbridge/intel/i855/raminit.h" +#include <southbridge/intel/i82801dx/i82801dx.h> +#include <northbridge/intel/i855/raminit.h> #include "northbridge/intel/i855/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c index 4df217f236..8260cde792 100644 --- a/src/mainboard/digitallogic/msm800sev/romstage.c +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -4,17 +4,17 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> #include <cpu/amd/car.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "northbridge/amd/lx/raminit.h" +#include <northbridge/amd/lx/raminit.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/dmp/vortex86ex/romstage.c b/src/mainboard/dmp/vortex86ex/romstage.c index d43df8d02c..5deebc5a65 100644 --- a/src/mainboard/dmp/vortex86ex/romstage.c +++ b/src/mainboard/dmp/vortex86ex/romstage.c @@ -25,10 +25,10 @@ #include <cpu/x86/cache.h> #include <halt.h> #include "drivers/pc80/i8254.c" -#include "northbridge/dmp/vortex86ex/northbridge.h" -#include "southbridge/dmp/vortex86ex/southbridge.h" +#include <northbridge/dmp/vortex86ex/northbridge.h> +#include <southbridge/dmp/vortex86ex/southbridge.h> #include "northbridge/dmp/vortex86ex/raminit.c" -#include "cpu/dmp/dmp_post_code.h" +#include <cpu/dmp/dmp_post_code.h> #define DMP_CPUID_SX 0x31504d44 #define DMP_CPUID_DX 0x32504d44 diff --git a/src/mainboard/ecs/p6iwp-fe/romstage.c b/src/mainboard/ecs/p6iwp-fe/romstage.c index 0ffcfa5ede..db699062d7 100644 --- a/src/mainboard/ecs/p6iwp-fe/romstage.c +++ b/src/mainboard/ecs/p6iwp-fe/romstage.c @@ -25,10 +25,10 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "southbridge/intel/i82801ax/i82801ax.h" -#include "northbridge/intel/i82810/raminit.h" +#include <southbridge/intel/i82801ax/i82801ax.h> +#include <northbridge/intel/i82810/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include <lib.h> diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index 8992a5773d..efa26473ab 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -28,7 +28,7 @@ #include <timestamp.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "memory.c" diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index 6f08b6af8f..0db9166936 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -29,7 +29,7 @@ #include <timestamp.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "../qemu-i440fx/memory.c" diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index b57e6b7be4..c4b053fc89 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -32,9 +32,9 @@ #include <console/console.h> #include <cpu/x86/bist.h> #include <halt.h> -#include "northbridge/intel/i945/i945.h" -#include "northbridge/intel/i945/raminit.h" -#include "southbridge/intel/i82801gx/i82801gx.h" +#include <northbridge/intel/i945/i945.h> +#include <northbridge/intel/i945/raminit.h> +#include <southbridge/intel/i82801gx/i82801gx.h> #include "option_table.h" void setup_ich7_gpios(void) diff --git a/src/mainboard/gigabyte/ga-6bxc/romstage.c b/src/mainboard/gigabyte/ga-6bxc/romstage.c index 9e465dd071..3897551e60 100644 --- a/src/mainboard/gigabyte/ga-6bxc/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxc/romstage.c @@ -24,11 +24,11 @@ #include <device/pnp_def.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/ite/it8671f/it8671f.h> #include <lib.h> diff --git a/src/mainboard/gigabyte/ga-6bxe/romstage.c b/src/mainboard/gigabyte/ga-6bxe/romstage.c index 369a23f0f3..995a65723c 100644 --- a/src/mainboard/gigabyte/ga-6bxe/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxe/romstage.c @@ -24,11 +24,11 @@ #include <device/pnp_def.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/ite/it8671f/it8671f.h> #include <lib.h> diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c index 6fea437c32..a1515eec04 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c @@ -30,10 +30,10 @@ #include <console/console.h> #include <superio/ite/it8728f/it8728f.h> #include <superio/ite/common/ite.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit_native.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 10bbb6f361..44fa4ca6b0 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -32,15 +32,15 @@ #include <console/console.h> #include <spd.h> #include <cpu/amd/model_fxx_rev.h> -#include "southbridge/sis/sis966/sis966.h" +#include <southbridge/sis/sis966/sis966.h> #include "southbridge/sis/sis966/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8716f/it8716f.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/sis/sis966/early_ctrl.c" @@ -56,7 +56,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/f.h" +#include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" @@ -78,7 +78,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ -#include "southbridge/sis/sis966/early_setup_ss.h" +#include <southbridge/sis/sis966/early_setup_ss.h> #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index b2e1d70477..da12a97c69 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -31,13 +31,13 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8716f/it8716f.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" @@ -61,9 +61,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ -#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" -#include "northbridge/amd/amdk8/f.h" +#include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 75090d9136..8d73b265fa 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -30,20 +30,20 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/smbus.h> #include "northbridge/amd/amdfam10/debug.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) @@ -56,12 +56,12 @@ static int spd_read_byte(u32 device, u32 address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 87778c6fca..c7094ae57f 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -30,20 +30,20 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/smbus.h> #include "northbridge/amd/amdfam10/debug.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) @@ -56,12 +56,12 @@ static int spd_read_byte(u32 device, u32 address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index b3ae3266b9..bbfe80b1e5 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -34,20 +34,20 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/smbus.h> #include "northbridge/amd/amdfam10/debug.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) @@ -60,12 +60,12 @@ static int spd_read_byte(u32 device, u32 address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index a0c3d28b85..f420bf2efe 100644 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -33,13 +33,13 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <cpu/x86/cache.h> #include <sb_cimx.h> #include "SBPLATFORM.h" #include "cbmem.h" -#include "cpu/amd/mtrr.h" -#include "cpu/amd/agesa/s3_resume.h" +#include <cpu/amd/mtrr.h> +#include <cpu/amd/agesa/s3_resume.h> #define MSR_MTRR_VARIABLE_BASE6 0x020C #define MSR_MTRR_VARIABLE_MASK6 0x020D diff --git a/src/mainboard/gizmosphere/gizmo2/romstage.c b/src/mainboard/gizmosphere/gizmo2/romstage.c index 82dcd602de..226278236f 100644 --- a/src/mainboard/gizmosphere/gizmo2/romstage.c +++ b/src/mainboard/gizmosphere/gizmo2/romstage.c @@ -31,10 +31,10 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" -#include "southbridge/amd/agesa/hudson/hudson.h" -#include "cpu/amd/agesa/s3_resume.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <southbridge/amd/agesa/hudson/hudson.h> +#include <cpu/amd/agesa/s3_resume.h> #include "cbmem.h" diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index 6cf86ada5a..70a6f444c7 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -31,10 +31,10 @@ #include <arch/acpi.h> #include <cbmem.h> #include <console/console.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index f58ab1359c..873de91321 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -32,10 +32,10 @@ #include <arch/acpi.h> #include <cbmem.h> #include <console/console.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> #include "ec/google/chromeec/ec.h" #include <arch/cpu.h> #include <cpu/x86/bist.h> diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 69711d9203..7d67abd181 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -31,10 +31,10 @@ #include <arch/acpi.h> #include <cbmem.h> #include <console/console.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/google/peppy/romstage.c b/src/mainboard/google/peppy/romstage.c index 38c224b2c0..9a1fb769a8 100644 --- a/src/mainboard/google/peppy/romstage.c +++ b/src/mainboard/google/peppy/romstage.c @@ -24,12 +24,12 @@ #include <string.h> #include <cbfs.h> #include <console/console.h> -#include "cpu/intel/haswell/haswell.h" +#include <cpu/intel/haswell/haswell.h> #include "ec/google/chromeec/ec.h" -#include "northbridge/intel/haswell/haswell.h" -#include "northbridge/intel/haswell/raminit.h" -#include "southbridge/intel/lynxpoint/pch.h" -#include "southbridge/intel/lynxpoint/lp_gpio.h" +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/lynxpoint/lp_gpio.h> #include "gpio.h" #include "onboard.h" diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index fd190ed714..6feebac28c 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -24,11 +24,11 @@ #include <string.h> #include <cbfs.h> #include <console/console.h> -#include "cpu/intel/haswell/haswell.h" -#include "northbridge/intel/haswell/haswell.h" -#include "northbridge/intel/haswell/raminit.h" -#include "southbridge/intel/lynxpoint/pch.h" -#include "southbridge/intel/lynxpoint/lp_gpio.h" +#include <cpu/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/lynxpoint/lp_gpio.h> #include "gpio.h" const struct rcba_config_instruction rcba_config[] = { diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index e8f2927526..f856c59d2f 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -31,10 +31,10 @@ #include <arch/acpi.h> #include <cbmem.h> #include <console/console.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index 2b42e73e8e..db3c3063eb 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -12,14 +12,14 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include <delay.h> -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "southbridge/amd/amd8111/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "southbridge/amd/amd8111/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 474f273781..008b353fde 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -36,13 +36,13 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "southbridge/broadcom/bcm5785/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/serverengines/pilot/pilot.h> #include <superio/nsc/pc87417/pc87417.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/broadcom/bcm5785/early_setup.c" @@ -66,7 +66,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/f.h" +#include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index e22ed1c48b..b2f4c10ffe 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -39,16 +39,16 @@ #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> #include "southbridge/broadcom/bcm5785/early_smbus.c" -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> #include <spd.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <superio/serverengines/pilot/pilot.h> #include <superio/nsc/pc87417/pc87417.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdfam10/debug.c" #include "southbridge/broadcom/bcm5785/early_setup.c" @@ -71,11 +71,11 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/hp/e_vectra_p2706t/romstage.c b/src/mainboard/hp/e_vectra_p2706t/romstage.c index f54e0e85aa..dcdd552caa 100644 --- a/src/mainboard/hp/e_vectra_p2706t/romstage.c +++ b/src/mainboard/hp/e_vectra_p2706t/romstage.c @@ -27,9 +27,9 @@ /* TODO: It's a PC87364 actually! */ #include <superio/nsc/pc87360/pc87360.h> /* TODO: It's i810E actually! */ -#include "northbridge/intel/i82810/raminit.h" -#include "cpu/x86/bist.h" -#include "southbridge/intel/i82801ax/i82801ax.h" +#include <northbridge/intel/i82810/raminit.h> +#include <cpu/x86/bist.h> +#include <southbridge/intel/i82801ax/i82801ax.h> #include "drivers/pc80/udelay_io.c" #include <lib.h> diff --git a/src/mainboard/ibm/e325/romstage.c b/src/mainboard/ibm/e325/romstage.c index 4e1e925e74..54a543d0f5 100644 --- a/src/mainboard/ibm/e325/romstage.c +++ b/src/mainboard/ibm/e325/romstage.c @@ -9,12 +9,12 @@ #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/nsc/pc87366/pc87366.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> #include "southbridge/amd/amd8111/early_ctrl.c" diff --git a/src/mainboard/ibm/e326/romstage.c b/src/mainboard/ibm/e326/romstage.c index 2ac90abf2e..794fd15a66 100644 --- a/src/mainboard/ibm/e326/romstage.c +++ b/src/mainboard/ibm/e326/romstage.c @@ -9,12 +9,12 @@ #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/nsc/pc87366/pc87366.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" #include <spd.h> diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 2182a7e779..3866f032fd 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -34,20 +34,20 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f71859/f71859.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/smbus.h> #include "northbridge/amd/amdfam10/debug.c" #define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1) @@ -59,12 +59,12 @@ static int spd_read_byte(u32 device, u32 address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c index b11f5cb7ca..401d362eca 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c +++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c @@ -24,16 +24,16 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "northbridge/amd/lx/raminit.h" +#include <northbridge/amd/lx/raminit.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index e02ae7aad1..7aea6b6eae 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -21,10 +21,10 @@ #include <stdint.h> #include <stddef.h> #include <console/console.h> -#include "cpu/intel/haswell/haswell.h" -#include "northbridge/intel/haswell/haswell.h" -#include "northbridge/intel/haswell/raminit.h" -#include "southbridge/intel/lynxpoint/pch.h" +#include <cpu/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> #include "gpio.h" const struct rcba_config_instruction rcba_config[] = { diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index a660df2a25..72832ea4cb 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -35,11 +35,11 @@ #include <reset.h> #include <superio/smsc/sio1007/chip.h> #include <fsp_util.h> -#include "northbridge/intel/fsp_sandybridge/northbridge.h" -#include "northbridge/intel/fsp_sandybridge/raminit.h" -#include "southbridge/intel/fsp_bd82x6x/pch.h" -#include "southbridge/intel/fsp_bd82x6x/gpio.h" -#include "southbridge/intel/fsp_bd82x6x/me.h" +#include <northbridge/intel/fsp_sandybridge/northbridge.h> +#include <northbridge/intel/fsp_sandybridge/raminit.h> +#include <southbridge/intel/fsp_bd82x6x/pch.h> +#include <southbridge/intel/fsp_bd82x6x/gpio.h> +#include <southbridge/intel/fsp_bd82x6x/me.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> #include "gpio.h" diff --git a/src/mainboard/intel/d810e2cb/romstage.c b/src/mainboard/intel/d810e2cb/romstage.c index a6958eeaae..e7b78f8052 100644 --- a/src/mainboard/intel/d810e2cb/romstage.c +++ b/src/mainboard/intel/d810e2cb/romstage.c @@ -24,10 +24,10 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "southbridge/intel/i82801bx/i82801bx.h" -#include "northbridge/intel/i82810/raminit.h" +#include <southbridge/intel/i82801bx/i82801bx.h> +#include <northbridge/intel/i82810/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #include "gpio.c" #include <lib.h> diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 4194a80aaa..c8b53ed188 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -32,9 +32,9 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> -#include "northbridge/intel/i945/i945.h" -#include "northbridge/intel/i945/raminit.h" -#include "southbridge/intel/i82801gx/i82801gx.h" +#include <northbridge/intel/i945/i945.h> +#include <northbridge/intel/i945/raminit.h> +#include <southbridge/intel/i82801gx/i82801gx.h> #define SERIAL_DEV PNP_DEV(0x2e, LPC47M15X_SP1) #define PME_DEV PNP_DEV(0x2e, LPC47M15X_PME) diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c index b41e0c5cae..b0efb7d0f2 100644 --- a/src/mainboard/intel/eagleheights/romstage.c +++ b/src/mainboard/intel/eagleheights/romstage.c @@ -35,8 +35,8 @@ #include "southbridge/intel/i3100/reset.c" #include <superio/intel/i3100/i3100.h> #include <superio/smsc/smscsuperio/smscsuperio.h> -#include "northbridge/intel/i3100/i3100.h" -#include "southbridge/intel/i3100/i3100.h" +#include <northbridge/intel/i3100/i3100.h> +#include <southbridge/intel/i3100/i3100.h> #include "lib/debug.c" // XXX #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0) @@ -67,7 +67,7 @@ static inline int spd_read_byte(u16 device, u8 address) return smbus_read_byte(device, address); } -#include "northbridge/intel/i3100/raminit.h" +#include <northbridge/intel/i3100/raminit.h> #include "northbridge/intel/i3100/memory_initialized.c" #include "northbridge/intel/i3100/raminit.c" #include "lib/generic_sdram.c" diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index ffb44a0423..adcf175d04 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -31,10 +31,10 @@ #include <cbmem.h> #include <console/console.h> #include <superio/smsc/sio1007/chip.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c index 959beab260..61f9a2c3cb 100644 --- a/src/mainboard/intel/mtarvon/romstage.c +++ b/src/mainboard/intel/mtarvon/romstage.c @@ -28,10 +28,10 @@ #include <console/console.h> #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" -#include "northbridge/intel/i3100/raminit.h" +#include <northbridge/intel/i3100/raminit.h> #include <superio/intel/i3100/i3100.h> #include "northbridge/intel/i3100/memory_initialized.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <spd.h> #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0) diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c index 4c15f672a0..5145a50ced 100644 --- a/src/mainboard/intel/truxton/romstage.c +++ b/src/mainboard/intel/truxton/romstage.c @@ -29,11 +29,11 @@ #include <console/console.h> #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" -#include "northbridge/intel/i3100/raminit_ep80579.h" +#include <northbridge/intel/i3100/raminit_ep80579.h> #include <superio/intel/i3100/i3100.h> #include "cpu/x86/mtrr/earlymtrr.c" #include "lib/debug.c" // XXX -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <spd.h> #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 | DEVPRES_D4F0) diff --git a/src/mainboard/iwave/iWRainbowG6/romstage.c b/src/mainboard/iwave/iWRainbowG6/romstage.c index 00d4a38c5a..6d9824f647 100644 --- a/src/mainboard/iwave/iWRainbowG6/romstage.c +++ b/src/mainboard/iwave/iWRainbowG6/romstage.c @@ -273,7 +273,7 @@ int selectcard(void) #endif #include "northbridge/intel/sch/early_init.c" -#include "northbridge/intel/sch/raminit.h" +#include <northbridge/intel/sch/raminit.h> #include "northbridge/intel/sch/raminit.c" static void sch_enable_lpc(void) diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index a42956823a..0e579ef5bd 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -8,9 +8,9 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "southbridge/amd/amd8111/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "northbridge/amd/amdk8/reset_test.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> @@ -54,7 +54,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c index d2371b526c..9a45217af9 100644 --- a/src/mainboard/iwill/dk8s2/romstage.c +++ b/src/mainboard/iwill/dk8s2/romstage.c @@ -8,9 +8,9 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "southbridge/amd/amd8111/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "northbridge/amd/amdk8/reset_test.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> @@ -54,7 +54,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c index 50869f7ca6..0525aa99d3 100644 --- a/src/mainboard/iwill/dk8x/romstage.c +++ b/src/mainboard/iwill/dk8x/romstage.c @@ -8,9 +8,9 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "southbridge/amd/amd8111/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "northbridge/amd/amdk8/reset_test.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> @@ -54,7 +54,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" diff --git a/src/mainboard/jetway/j7f2/romstage.c b/src/mainboard/jetway/j7f2/romstage.c index a66467b8f1..ca7edad278 100644 --- a/src/mainboard/jetway/j7f2/romstage.c +++ b/src/mainboard/jetway/j7f2/romstage.c @@ -25,8 +25,8 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "northbridge/via/cn700/raminit.h" -#include "cpu/x86/bist.h" +#include <northbridge/via/cn700/raminit.h> +#include <cpu/x86/bist.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "southbridge/via/vt8237r/early_smbus.c" diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 87af9790bd..97584e73a9 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -35,20 +35,20 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f71863fg/f71863fg.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/smbus.h> #include "northbridge/amd/amdfam10/debug.c" #if CONFIG_TTYS0_BASE == 0x2f8 @@ -64,12 +64,12 @@ static int spd_read_byte(u32 device, u32 address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 652d8cb7c4..e72c3dcceb 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -34,9 +34,9 @@ #include <cpu/x86/bist.h> #include <halt.h> #include <superio/winbond/w83627thg/w83627thg.h> -#include "northbridge/intel/i945/i945.h" -#include "northbridge/intel/i945/raminit.h" -#include "southbridge/intel/i82801gx/i82801gx.h" +#include <northbridge/intel/i945/i945.h> +#include <northbridge/intel/i945/raminit.h> +#include <southbridge/intel/i82801gx/i82801gx.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index 24cae41bde..e4ef4590c3 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -27,16 +27,16 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include <spd.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> #include <cpu/amd/mtrr.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" @@ -49,7 +49,7 @@ static inline int spd_read_byte(u32 device, u32 address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 6926952e8c..31f1b22a0f 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -30,10 +30,10 @@ #include <arch/acpi.h> #include <cbmem.h> #include <console/console.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/lanner/em8510/romstage.c b/src/mainboard/lanner/em8510/romstage.c index c1a02f4f0d..0216001e33 100644 --- a/src/mainboard/lanner/em8510/romstage.c +++ b/src/mainboard/lanner/em8510/romstage.c @@ -30,12 +30,12 @@ #include "drivers/pc80/udelay_io.c" #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "southbridge/intel/i82801dx/i82801dx.h" -#include "northbridge/intel/i855/raminit.h" +#include <southbridge/intel/i82801dx/i82801dx.h> +#include <northbridge/intel/i855/raminit.h> #include "northbridge/intel/i855/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627thg/w83627thg.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index 0a49ed05c3..fbf47ac9ca 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -24,8 +24,8 @@ #include <arch/io.h> #include <device/pci_def.h> #include <console/console.h> -#include "northbridge/intel/sandybridge/raminit_native.h" -#include "southbridge/intel/bd82x6x/pch.h" +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> void pch_enable_lpc(void) { diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 571a21cfd6..094e1dc105 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -36,9 +36,9 @@ #include <console/console.h> #include <cpu/x86/bist.h> #include <halt.h> -#include "northbridge/intel/i945/i945.h" -#include "northbridge/intel/i945/raminit.h" -#include "southbridge/intel/i82801gx/i82801gx.h" +#include <northbridge/intel/i945/i945.h> +#include <northbridge/intel/i945/raminit.h> +#include <southbridge/intel/i82801gx/i82801gx.h> #include "dock.h" void setup_ich7_gpios(void) diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index be49067736..64011b1f6e 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -42,11 +42,11 @@ #include "gpio.h" #include "dock.h" #include "arch/early_variables.h" -#include "southbridge/intel/ibexpeak/pch.h" -#include "northbridge/intel/nehalem/nehalem.h" +#include <southbridge/intel/ibexpeak/pch.h> +#include <northbridge/intel/nehalem/nehalem.h> -#include "northbridge/intel/nehalem/raminit.h" -#include "southbridge/intel/ibexpeak/me.h" +#include <northbridge/intel/nehalem/raminit.h> +#include <southbridge/intel/ibexpeak/me.h> static void pch_enable_lpc(void) { diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index d9c8aa04e1..d0fb8e6abc 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -30,10 +30,10 @@ #include <cpu/x86/lapic.h> #include <arch/acpi.h> #include <console/console.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit_native.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 0bb137e732..4ea272d381 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -32,10 +32,10 @@ #include <arch/acpi.h> #include <cbmem.h> #include <console/console.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit_native.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cbfs.h> diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index af9b1be653..b9976377b2 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -36,9 +36,9 @@ #include <console/console.h> #include <cpu/x86/bist.h> #include <halt.h> -#include "northbridge/intel/i945/i945.h" -#include "northbridge/intel/i945/raminit.h" -#include "southbridge/intel/i82801gx/i82801gx.h" +#include <northbridge/intel/i945/i945.h> +#include <northbridge/intel/i945/raminit.h> +#include <southbridge/intel/i82801gx/i82801gx.h> #include "dock.h" void setup_ich7_gpios(void) diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index d21a5658cc..0f718f2da6 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -32,15 +32,15 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include <cpu/x86/cache.h> #include <sb_cimx.h> #include "SBPLATFORM.h" #include "cbmem.h" -#include "cpu/amd/mtrr.h" -#include "cpu/amd/agesa/s3_resume.h" +#include <cpu/amd/mtrr.h> +#include <cpu/amd/agesa/s3_resume.h> #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c index 3be4eb3d1c..f86d5580b5 100644 --- a/src/mainboard/lippert/frontrunner/romstage.c +++ b/src/mainboard/lippert/frontrunner/romstage.c @@ -6,10 +6,10 @@ #include <console/console.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/gx2def.h> -#include "southbridge/amd/cs5535/cs5535.h" +#include <southbridge/amd/cs5535/cs5535.h> #include "southbridge/amd/cs5535/early_smbus.c" #include "southbridge/amd/cs5535/early_setup.c" @@ -62,7 +62,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return (address < sizeof(spdbytes)) ? spdbytes[address] : 0xFF; } -#include "northbridge/amd/gx2/raminit.h" +#include <northbridge/amd/gx2/raminit.h> #include "northbridge/amd/gx2/pll_reset.c" #include "northbridge/amd/gx2/raminit.c" #include "lib/generic_sdram.c" diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c index 416a8fb9fa..8e802f3bee 100644 --- a/src/mainboard/lippert/hurricane-lx/romstage.c +++ b/src/mainboard/lippert/hurricane-lx/romstage.c @@ -27,16 +27,16 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> -#include "northbridge/amd/lx/raminit.h" +#include <northbridge/amd/lx/raminit.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c index 8b48640306..919977263e 100644 --- a/src/mainboard/lippert/literunner-lx/romstage.c +++ b/src/mainboard/lippert/literunner-lx/romstage.c @@ -28,15 +28,15 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> -#include "northbridge/amd/lx/raminit.h" +#include <northbridge/amd/lx/raminit.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c index 4d8a6fd443..dc503ed9ce 100644 --- a/src/mainboard/lippert/roadrunner-lx/romstage.c +++ b/src/mainboard/lippert/roadrunner-lx/romstage.c @@ -27,16 +27,16 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> -#include "northbridge/amd/lx/raminit.h" +#include <northbridge/amd/lx/raminit.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c index 3c25c084d9..2a22140063 100644 --- a/src/mainboard/lippert/spacerunner-lx/romstage.c +++ b/src/mainboard/lippert/spacerunner-lx/romstage.c @@ -28,15 +28,15 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> -#include "northbridge/amd/lx/raminit.h" +#include <northbridge/amd/lx/raminit.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index e655f9a78a..415cdbee13 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -32,16 +32,16 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include <cpu/x86/cache.h> #include <sb_cimx.h> #include "SBPLATFORM.h" #include "cbmem.h" -#include "cpu/amd/mtrr.h" -#include "cpu/amd/agesa/s3_resume.h" +#include <cpu/amd/mtrr.h> +#include <cpu/amd/agesa/s3_resume.h> #define SERIAL_DEV PNP_DEV(0x4e, W83627DHG_SP1) diff --git a/src/mainboard/mitac/6513wu/romstage.c b/src/mainboard/mitac/6513wu/romstage.c index 2710082bb0..c157c99972 100644 --- a/src/mainboard/mitac/6513wu/romstage.c +++ b/src/mainboard/mitac/6513wu/romstage.c @@ -24,11 +24,11 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "southbridge/intel/i82801ax/i82801ax.h" -#include "northbridge/intel/i82810/raminit.h" +#include <southbridge/intel/i82801ax/i82801ax.h> +#include <northbridge/intel/i82810/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #include <lib.h> diff --git a/src/mainboard/msi/ms6119/romstage.c b/src/mainboard/msi/ms6119/romstage.c index fb30e49fed..d3a51e4878 100644 --- a/src/mainboard/msi/ms6119/romstage.c +++ b/src/mainboard/msi/ms6119/romstage.c @@ -24,11 +24,11 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> #include <lib.h> diff --git a/src/mainboard/msi/ms6147/romstage.c b/src/mainboard/msi/ms6147/romstage.c index 916f0e9aa2..95780bfc23 100644 --- a/src/mainboard/msi/ms6147/romstage.c +++ b/src/mainboard/msi/ms6147/romstage.c @@ -24,8 +24,8 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include <cpu/x86/bist.h> diff --git a/src/mainboard/msi/ms6156/romstage.c b/src/mainboard/msi/ms6156/romstage.c index e8dbb02993..9073be185b 100644 --- a/src/mainboard/msi/ms6156/romstage.c +++ b/src/mainboard/msi/ms6156/romstage.c @@ -24,11 +24,11 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> #include <lib.h> diff --git a/src/mainboard/msi/ms6178/romstage.c b/src/mainboard/msi/ms6178/romstage.c index 66a9c9bf74..50590747c8 100644 --- a/src/mainboard/msi/ms6178/romstage.c +++ b/src/mainboard/msi/ms6178/romstage.c @@ -26,9 +26,9 @@ #include <console/console.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "northbridge/intel/i82810/raminit.h" -#include "cpu/x86/bist.h" -#include "southbridge/intel/i82801ax/i82801ax.h" +#include <northbridge/intel/i82810/raminit.h> +#include <cpu/x86/bist.h> +#include <southbridge/intel/i82801ax/i82801ax.h> #include "drivers/pc80/udelay_io.c" #include <lib.h> diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index 15c02f595c..290423b8ec 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -29,18 +29,18 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627thg/w83627thg.h> #include <cpu/amd/model_fxx_rev.h> #include <console/console.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/nvidia/ck804/early_smbus.h" -#include "northbridge/amd/amdk8/raminit.h" +#include <southbridge/nvidia/ck804/early_smbus.h> +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/debug.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "cpu/amd/dualcore/dualcore.c" @@ -62,7 +62,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit.c" #include "lib/generic_sdram.c" -#include "southbridge/nvidia/ck804/early_setup_ss.h" +#include <southbridge/nvidia/ck804/early_setup_ss.h> #include "southbridge/nvidia/ck804/early_setup_car.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index fd8fbfb2b5..96381e77c8 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -31,15 +31,15 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include <lib.h> #include <spd.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" @@ -54,7 +54,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/f.h" +#include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" @@ -70,7 +70,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ -#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index bd8243650a..142a496da2 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -34,14 +34,14 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "southbridge/broadcom/bcm5785/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include <reset.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/nsc/pc87417/pc87417.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/broadcom/bcm5785/early_setup.c" @@ -64,7 +64,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/f.h" +#include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index 9a6e21fc3a..d607a7d2e9 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -32,14 +32,14 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <spd.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include <device/pci_ids.h> @@ -63,14 +63,14 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/f.h" +#include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" -#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include <southbridge/nvidia/mcp55/early_setup_ss.h> //set GPIO to input mode #define MCP55_MB_SETUP \ diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 722122d19c..9cc3640fc9 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -34,14 +34,14 @@ #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" @@ -55,7 +55,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" @@ -69,9 +69,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ -#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/nec/powermate2000/romstage.c b/src/mainboard/nec/powermate2000/romstage.c index 6bbfc1a0bf..f13f746083 100644 --- a/src/mainboard/nec/powermate2000/romstage.c +++ b/src/mainboard/nec/powermate2000/romstage.c @@ -25,9 +25,9 @@ #include <stdlib.h> #include <console/console.h> #include <superio/smsc/smscsuperio/smscsuperio.h> -#include "northbridge/intel/i82810/raminit.h" -#include "cpu/x86/bist.h" -#include "southbridge/intel/i82801ax/i82801ax.h" +#include <northbridge/intel/i82810/raminit.h> +#include <cpu/x86/bist.h> +#include <southbridge/intel/i82801ax/i82801ax.h> #include "drivers/pc80/udelay_io.c" #include <lib.h> diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c index b34882efae..0f7d943393 100644 --- a/src/mainboard/newisys/khepri/romstage.c +++ b/src/mainboard/newisys/khepri/romstage.c @@ -16,13 +16,13 @@ #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" diff --git a/src/mainboard/nokia/ip530/romstage.c b/src/mainboard/nokia/ip530/romstage.c index 3c5511b48b..2fc5cbe2e1 100644 --- a/src/mainboard/nokia/ip530/romstage.c +++ b/src/mainboard/nokia/ip530/romstage.c @@ -24,11 +24,11 @@ #include <device/pnp_def.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #include <lib.h> diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index df78a0c622..982b7756b1 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -32,13 +32,13 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" @@ -53,7 +53,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/f.h" +#include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" @@ -69,7 +69,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ -#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index fbbd4b5aad..a366d387ca 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -41,11 +41,11 @@ #include <cpu/intel/romstage.h> #include "arch/early_variables.h" -#include "southbridge/intel/ibexpeak/pch.h" -#include "northbridge/intel/nehalem/nehalem.h" +#include <southbridge/intel/ibexpeak/pch.h> +#include <northbridge/intel/nehalem/nehalem.h> -#include "northbridge/intel/nehalem/raminit.h" -#include "southbridge/intel/ibexpeak/me.h" +#include <northbridge/intel/nehalem/raminit.h> +#include <southbridge/intel/ibexpeak/me.h> static void pch_enable_lpc(void) { diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index f4bbc317fb..38541e7c51 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -25,12 +25,12 @@ #include <device/pnp_def.h> #include <console/console.h> #include <lib.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> #include <cpu/amd/car.h> -#include "southbridge/amd/cs5536/cs5536.h" -#include "northbridge/amd/lx/raminit.h" +#include <southbridge/amd/cs5536/cs5536.h> +#include <northbridge/amd/lx/raminit.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index 1316d5ec9d..6f62311b00 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -25,12 +25,12 @@ #include <device/pnp_def.h> #include <console/console.h> #include <lib.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> #include <cpu/amd/car.h> -#include "southbridge/amd/cs5536/cs5536.h" -#include "northbridge/amd/lx/raminit.h" +#include <southbridge/amd/cs5536/cs5536.h> +#include <northbridge/amd/lx/raminit.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c index 500416ae1e..9da69b5338 100644 --- a/src/mainboard/rca/rm4100/romstage.c +++ b/src/mainboard/rca/rm4100/romstage.c @@ -27,11 +27,11 @@ #include <console/console.h> #include <lib.h> #include <superio/smsc/smscsuperio/smscsuperio.h> -#include "northbridge/intel/i82830/raminit.h" +#include <northbridge/intel/i82830/raminit.h> #include "northbridge/intel/i82830/memory_initialized.c" -#include "southbridge/intel/i82801dx/i82801dx.h" +#include <southbridge/intel/i82801dx/i82801dx.h> #include "southbridge/intel/i82801dx/reset.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "spd_table.h" #include "gpio.c" #include "southbridge/intel/i82801dx/tco_timer.c" diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index e8ada36d78..a7fd007a3e 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -34,9 +34,9 @@ #include <console/console.h> #include <cpu/x86/bist.h> #include <halt.h> -#include "northbridge/intel/i945/i945.h" -#include "northbridge/intel/i945/raminit.h" -#include "southbridge/intel/i82801gx/i82801gx.h" +#include <northbridge/intel/i945/i945.h> +#include <northbridge/intel/i945/raminit.h> +#include <southbridge/intel/i82801gx/i82801gx.h> #include "option_table.h" void setup_ich7_gpios(void) diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 8568f8428a..a8c1249458 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -33,10 +33,10 @@ #include <cbmem.h> #include <console/console.h> #include <bootmode.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 2ed185baf9..c5c2095da2 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -34,10 +34,10 @@ #include <bootmode.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8772f/it8772f.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index 4beb8c95b6..5599a24811 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -30,15 +30,15 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -65,7 +65,7 @@ static inline int spd_read_byte(u32 device, u32 address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c index 531e2236f2..ca02936b91 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c +++ b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c @@ -24,11 +24,11 @@ #include <device/pnp_def.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/ite/it8671f/it8671f.h> #include <lib.h> diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index 99d0dfb7be..8c4724fc25 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -10,14 +10,14 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/nvidia/ck804/early_smbus.h" -#include "northbridge/amd/amdk8/raminit.h" +#include <southbridge/nvidia/ck804/early_smbus.h> +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/smsc/lpc47b397/lpc47b397.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "superio/smsc/lpc47b397/early_gpio.c" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -51,7 +51,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" -#include "southbridge/nvidia/ck804/early_setup_ss.h" +#include <southbridge/nvidia/ck804/early_setup_ss.h> //set GPIO to input mode #define CK804_MB_SETUP \ diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index e3e738674e..21355634ab 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -29,13 +29,13 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" @@ -62,14 +62,14 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/f.h" +#include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" -#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index 7d1f834a7c..84198d2168 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -32,13 +32,13 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" @@ -54,14 +54,14 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/f.h" +#include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" -#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 08c7d2b309..a6bb53c35c 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -34,14 +34,14 @@ #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" @@ -56,14 +56,14 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index c231e31301..07c3c3375e 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -24,11 +24,11 @@ #include <arch/cpu.h> #include <console/console.h> #include <arch/stages.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "northbridge/amd/agesa/family10/reset_test.h" +#include <northbridge/amd/agesa/family10/reset_test.h> #include <nb_cimx.h> #include <sb_cimx.h> #include <superio/nuvoton/wpcm450/wpcm450.h> diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index f46b2e631a..3fdd254340 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -34,14 +34,14 @@ #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" @@ -62,14 +62,14 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c index 0bbd8bc44d..ed82a38135 100644 --- a/src/mainboard/supermicro/h8scm/romstage.c +++ b/src/mainboard/supermicro/h8scm/romstage.c @@ -24,11 +24,11 @@ #include <arch/cpu.h> #include <console/console.h> #include <arch/stages.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "northbridge/amd/agesa/family10/reset_test.h" +#include <northbridge/amd/agesa/family10/reset_test.h> #include <nb_cimx.h> #include <sb_cimx.h> #include <superio/nuvoton/wpcm450/wpcm450.h> diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index 350ab1679e..dc5b2964e5 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -34,18 +34,18 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" -#include "southbridge/amd/sr5650/sr5650.h" +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/smbus.h> +#include <southbridge/amd/sr5650/sr5650.h> #include <superio/nuvoton/wpcm450/wpcm450.h> #include "northbridge/amd/amdfam10/debug.c" @@ -58,12 +58,12 @@ static int spd_read_byte(u32 device, u32 address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" #include <spd.h> diff --git a/src/mainboard/supermicro/x7db8/romstage.c b/src/mainboard/supermicro/x7db8/romstage.c index 83e34b5342..b4364a3c21 100644 --- a/src/mainboard/supermicro/x7db8/romstage.c +++ b/src/mainboard/supermicro/x7db8/romstage.c @@ -32,8 +32,8 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <northbridge/intel/i5000/raminit.h> -#include "northbridge/intel/i3100/i3100.h" -#include "southbridge/intel/i3100/i3100.h" +#include <northbridge/intel/i3100/i3100.h> +#include <southbridge/intel/i3100/i3100.h> #include <southbridge/intel/i3100/early_smbus.c> #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0) diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index 68373b9676..25ccd6e70f 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -26,15 +26,15 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include <spd.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" @@ -50,7 +50,7 @@ static inline int spd_read_byte(u32 device, u32 address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index 0ba0fce969..6cecf1894f 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -26,15 +26,15 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include <spd.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" @@ -50,7 +50,7 @@ static inline int spd_read_byte(u32 device, u32 address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/thomson/ip1000/romstage.c b/src/mainboard/thomson/ip1000/romstage.c index ede49f7ac1..5627296870 100644 --- a/src/mainboard/thomson/ip1000/romstage.c +++ b/src/mainboard/thomson/ip1000/romstage.c @@ -27,11 +27,11 @@ #include <console/console.h> #include <lib.h> #include <superio/smsc/smscsuperio/smscsuperio.h> -#include "northbridge/intel/i82830/raminit.h" +#include <northbridge/intel/i82830/raminit.h> #include "northbridge/intel/i82830/memory_initialized.c" -#include "southbridge/intel/i82801dx/i82801dx.h" +#include <southbridge/intel/i82801dx/i82801dx.h> #include "southbridge/intel/i82801dx/reset.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "spd_table.h" #include "gpio.c" #include "southbridge/intel/i82801dx/tco_timer.c" diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c index 76e4a5c883..12265181e9 100644 --- a/src/mainboard/traverse/geos/romstage.c +++ b/src/mainboard/traverse/geos/romstage.c @@ -25,14 +25,14 @@ #include <device/pnp_def.h> #include <console/console.h> #include <lib.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "northbridge/amd/lx/raminit.h" +#include <northbridge/amd/lx/raminit.h> int spd_read_byte(unsigned int device, unsigned int address) { diff --git a/src/mainboard/tyan/s1846/romstage.c b/src/mainboard/tyan/s1846/romstage.c index 10af34da25..201e6860b3 100644 --- a/src/mainboard/tyan/s1846/romstage.c +++ b/src/mainboard/tyan/s1846/romstage.c @@ -24,11 +24,11 @@ #include <device/pnp_def.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/nsc/pc87309/pc87309.h> #include <lib.h> diff --git a/src/mainboard/tyan/s2735/romstage.c b/src/mainboard/tyan/s2735/romstage.c index 5d4fd0e780..514aa61eb0 100644 --- a/src/mainboard/tyan/s2735/romstage.c +++ b/src/mainboard/tyan/s2735/romstage.c @@ -9,11 +9,11 @@ #include <lib.h> #include <spd.h> #include "southbridge/intel/i82801ex/early_smbus.c" -#include "northbridge/intel/e7501/raminit.h" +#include <northbridge/intel/e7501/raminit.h> #include "northbridge/intel/e7501/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c index 952b19d702..c6d3734c98 100644 --- a/src/mainboard/tyan/s2850/romstage.c +++ b/src/mainboard/tyan/s2850/romstage.c @@ -11,13 +11,13 @@ #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c index 8f87257814..ea2f4eb01b 100644 --- a/src/mainboard/tyan/s2875/romstage.c +++ b/src/mainboard/tyan/s2875/romstage.c @@ -11,13 +11,13 @@ #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" diff --git a/src/mainboard/tyan/s2880/romstage.c b/src/mainboard/tyan/s2880/romstage.c index 873652b503..0e1ac98303 100644 --- a/src/mainboard/tyan/s2880/romstage.c +++ b/src/mainboard/tyan/s2880/romstage.c @@ -11,13 +11,13 @@ #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c index c020f3eaf1..acfcec37b9 100644 --- a/src/mainboard/tyan/s2881/romstage.c +++ b/src/mainboard/tyan/s2881/romstage.c @@ -10,13 +10,13 @@ #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" diff --git a/src/mainboard/tyan/s2882/romstage.c b/src/mainboard/tyan/s2882/romstage.c index 873652b503..0e1ac98303 100644 --- a/src/mainboard/tyan/s2882/romstage.c +++ b/src/mainboard/tyan/s2882/romstage.c @@ -11,13 +11,13 @@ #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c index df602ea263..d321a453e7 100644 --- a/src/mainboard/tyan/s2885/romstage.c +++ b/src/mainboard/tyan/s2885/romstage.c @@ -10,13 +10,13 @@ #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" diff --git a/src/mainboard/tyan/s2891/romstage.c b/src/mainboard/tyan/s2891/romstage.c index e97b026c99..4856d461ea 100644 --- a/src/mainboard/tyan/s2891/romstage.c +++ b/src/mainboard/tyan/s2891/romstage.c @@ -10,15 +10,15 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/nvidia/ck804/early_smbus.h" -#include "northbridge/amd/amdk8/raminit.h" +#include <southbridge/nvidia/ck804/early_smbus.h> +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -37,7 +37,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" -#include "southbridge/nvidia/ck804/early_setup_ss.h" +#include <southbridge/nvidia/ck804/early_setup_ss.h> #include "southbridge/nvidia/ck804/early_setup.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/mainboard/tyan/s2892/romstage.c b/src/mainboard/tyan/s2892/romstage.c index 57da0724f9..4e11a1f58c 100644 --- a/src/mainboard/tyan/s2892/romstage.c +++ b/src/mainboard/tyan/s2892/romstage.c @@ -10,15 +10,15 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/nvidia/ck804/early_smbus.h" -#include "northbridge/amd/amdk8/raminit.h" +#include <southbridge/nvidia/ck804/early_smbus.h> +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -36,7 +36,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" -#include "southbridge/nvidia/ck804/early_setup_ss.h" +#include <southbridge/nvidia/ck804/early_setup_ss.h> //set GPIO to input mode #define CK804_MB_SETUP \ diff --git a/src/mainboard/tyan/s2895/romstage.c b/src/mainboard/tyan/s2895/romstage.c index 0e42f76974..b2fe6fd341 100644 --- a/src/mainboard/tyan/s2895/romstage.c +++ b/src/mainboard/tyan/s2895/romstage.c @@ -10,14 +10,14 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/nvidia/ck804/early_smbus.h" -#include "northbridge/amd/amdk8/raminit.h" +#include <southbridge/nvidia/ck804/early_smbus.h> +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/smsc/lpc47b397/lpc47b397.h> #include "superio/smsc/lpc47b397/early_gpio.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -51,7 +51,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" -#include "southbridge/nvidia/ck804/early_setup_ss.h" +#include <southbridge/nvidia/ck804/early_setup_ss.h> //set GPIO to input mode #define CK804_MB_SETUP \ diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index 55cb95e7d0..f62e5166f1 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -32,13 +32,13 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" @@ -53,7 +53,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/f.h" +#include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" @@ -69,7 +69,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ -#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 3e0f8f3dbb..77173adb0a 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -34,14 +34,14 @@ #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" @@ -55,7 +55,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" @@ -69,9 +69,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ -#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c index c106b1ceaa..53432af23b 100644 --- a/src/mainboard/tyan/s4880/romstage.c +++ b/src/mainboard/tyan/s4880/romstage.c @@ -10,13 +10,13 @@ #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c index 17379b5ac2..c0a3918194 100644 --- a/src/mainboard/tyan/s4882/romstage.c +++ b/src/mainboard/tyan/s4882/romstage.c @@ -9,13 +9,13 @@ #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index ac28874a30..e14292e061 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -24,11 +24,11 @@ #include <arch/cpu.h> #include <console/console.h> #include <arch/stages.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "northbridge/amd/agesa/family10/reset_test.h" +#include <northbridge/amd/agesa/family10/reset_test.h> #include <nb_cimx.h> #include <sb_cimx.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c index 8a0d384cad..373756faea 100644 --- a/src/mainboard/via/epia-cn/romstage.c +++ b/src/mainboard/via/epia-cn/romstage.c @@ -26,8 +26,8 @@ #include <device/pnp_def.h> #include <console/console.h> #include <lib.h> -#include "northbridge/via/cn700/raminit.h" -#include "cpu/x86/bist.h" +#include <northbridge/via/cn700/raminit.h> +#include <cpu/x86/bist.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "southbridge/via/vt8237r/early_smbus.c" diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index c9b1e8b1c0..8f64949c8f 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -32,14 +32,14 @@ #include <device/pnp_def.h> #include <console/console.h> #include <lib.h> -#include "northbridge/via/vx800/vx800.h" -#include "cpu/x86/bist.h" +#include <northbridge/via/vx800/vx800.h> +#include <cpu/x86/bist.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include <string.h> /* This file contains the board-special SI value for raminit.c. */ #include "driving_clk_phase_data.c" -#include "northbridge/via/vx800/raminit.h" +#include <northbridge/via/vx800/raminit.h> #include "northbridge/via/vx800/raminit.c" #include "wakeup.h" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c index 01d955a225..b2244cfac3 100644 --- a/src/mainboard/via/epia-m850/romstage.c +++ b/src/mainboard/via/epia-m850/romstage.c @@ -33,8 +33,8 @@ #include <timestamp.h> #include <console/cbmem_console.h> -#include "northbridge/via/vx900/early_vx900.h" -#include "northbridge/via/vx900/raminit.h" +#include <northbridge/via/vx900/early_vx900.h> +#include <northbridge/via/vx900/raminit.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c index 57e5cd09a3..7261e20a3d 100644 --- a/src/mainboard/via/pc2500e/romstage.c +++ b/src/mainboard/via/pc2500e/romstage.c @@ -26,8 +26,8 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <lib.h> -#include "northbridge/via/cn700/raminit.h" -#include "cpu/x86/bist.h" +#include <northbridge/via/cn700/raminit.h> +#include <cpu/x86/bist.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "southbridge/via/vt8237r/early_smbus.c" diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c index bb2d8789cd..8204ae384d 100644 --- a/src/mainboard/via/vt8454c/romstage.c +++ b/src/mainboard/via/vt8454c/romstage.c @@ -26,8 +26,8 @@ #include <device/pnp_def.h> #include <console/console.h> #include <lib.h> -#include "northbridge/via/cx700/raminit.h" -#include "cpu/x86/bist.h" +#include <northbridge/via/cx700/raminit.h> +#include <cpu/x86/bist.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "northbridge/via/cx700/early_smbus.c" diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c index a725beba83..7be35f9a30 100644 --- a/src/mainboard/winent/mb6047/romstage.c +++ b/src/mainboard/winent/mb6047/romstage.c @@ -10,15 +10,15 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/nvidia/ck804/early_smbus.h" -#include "northbridge/amd/amdk8/raminit.h" +#include <southbridge/nvidia/ck804/early_smbus.h> +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627thg/w83627thg.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) @@ -36,7 +36,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" #include "cpu/amd/dualcore/dualcore.c" -#include "southbridge/nvidia/ck804/early_setup_ss.h" +#include <southbridge/nvidia/ck804/early_setup_ss.h> #include "southbridge/nvidia/ck804/early_setup.c" #include "cpu/amd/model_fxx/init_cpus.c" #if CONFIG_SET_FIDVID diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c index 56b13296a1..ff68a8ce1c 100644 --- a/src/mainboard/winent/pl6064/romstage.c +++ b/src/mainboard/winent/pl6064/romstage.c @@ -26,16 +26,16 @@ #include <device/pnp_def.h> #include <console/console.h> #include <lib.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "northbridge/amd/lx/raminit.h" +#include <northbridge/amd/lx/raminit.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/wyse/s50/romstage.c b/src/mainboard/wyse/s50/romstage.c index 6283c9c0de..fea26cfd9c 100644 --- a/src/mainboard/wyse/s50/romstage.c +++ b/src/mainboard/wyse/s50/romstage.c @@ -25,8 +25,8 @@ #include <device/pnp_def.h> #include <console/console.h> #include <lib.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/gx2def.h> #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" @@ -40,7 +40,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#include "northbridge/amd/gx2/raminit.h" +#include <northbridge/amd/gx2/raminit.h> #include "northbridge/amd/gx2/pll_reset.c" #include "northbridge/amd/gx2/raminit.c" #include "lib/generic_sdram.c" |