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authorMartin Roth <martin.roth@se-eng.com>2014-12-07 14:59:46 -0700
committerMartin Roth <gaumless@gmail.com>2014-12-08 05:40:01 +0100
commit7c96629e94a0e37d8bb565f19d3c20865da50bec (patch)
treed0552a34faf40aef873ed8a0173e8a69125bde14 /src
parent1fc2ba5e6d85f3c7eef00a7e6b0b3ee1352fbfa9 (diff)
downloadcoreboot-7c96629e94a0e37d8bb565f19d3c20865da50bec.tar.xz
intel/fsp_baytrail: Spelling fixes
Change-Id: Ica9e3a91718a7e490ff80e5029fc29650355eb47 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7704 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/fsp_baytrail/Kconfig1
-rw-r--r--src/soc/intel/fsp_baytrail/baytrail/iosf.h4
-rw-r--r--src/soc/intel/fsp_baytrail/smihandler.c2
-rw-r--r--src/soc/intel/fsp_baytrail/spi.c2
4 files changed, 5 insertions, 4 deletions
diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig
index 85b3d3255b..caa01bdabc 100644
--- a/src/soc/intel/fsp_baytrail/Kconfig
+++ b/src/soc/intel/fsp_baytrail/Kconfig
@@ -50,6 +50,7 @@ config CPU_SPECIFIC_OPTIONS
select SUPPORT_CPU_UCODE_IN_CBFS if INCLUDE_MICROCODE_IN_BUILD
select CPU_MICROCODE_ADDED_DURING_BUILD if INCLUDE_MICROCODE_IN_BUILD
select ROMSTAGE_RTC_INIT
+ select BROKEN_CAR_MIGRATE
config BOOTBLOCK_CPU_INIT
string
diff --git a/src/soc/intel/fsp_baytrail/baytrail/iosf.h b/src/soc/intel/fsp_baytrail/baytrail/iosf.h
index 8fd1e24384..976e4acd02 100644
--- a/src/soc/intel/fsp_baytrail/baytrail/iosf.h
+++ b/src/soc/intel/fsp_baytrail/baytrail/iosf.h
@@ -59,7 +59,7 @@ uint32_t iosf_bunit_read(int reg);
void iosf_bunit_write(int reg, uint32_t val);
uint32_t iosf_dunit_read(int reg);
void iosf_dunit_write(int reg, uint32_t val);
-/* Some registers are per channel while the gloals live in dunit 0 */
+/* Some registers are per channel while the globals live in dunit 0 */
uint32_t iosf_dunit_ch0_read(int reg);
uint32_t iosf_dunit_ch1_read(int reg);
uint32_t iosf_punit_read(int reg);
@@ -69,7 +69,7 @@ void iosf_lpss_write(int reg, uint32_t val);
/* IOSF ports. */
#define IOSF_PORT_AUNIT 0x00 /* IO Arbiter unit */
#define IOSF_PORT_SYSMEMC 0x01 /* System Memory Controller */
-#define IOSF_PORT_BUNIT 0x03 /* System Memroy Arbiter/Bunit */
+#define IOSF_PORT_BUNIT 0x03 /* System Memory Arbiter/Bunit */
#define IOSF_PORT_DUNIT_CH1 0x07 /* DUNIT Channel 1 */
#define IOSF_PORT_USBPHY 0x43 /* USB PHY */
#define IOSF_PORT_USHPHY 0x61 /* USB XHCI PHY */
diff --git a/src/soc/intel/fsp_baytrail/smihandler.c b/src/soc/intel/fsp_baytrail/smihandler.c
index 234a34f4e3..d78288c1ca 100644
--- a/src/soc/intel/fsp_baytrail/smihandler.c
+++ b/src/soc/intel/fsp_baytrail/smihandler.c
@@ -395,7 +395,7 @@ void southbridge_smi_handler(void)
southbridge_smi[i]();
} else {
printk(BIOS_DEBUG,
- "SMI_STS[%d] occured, but no "
+ "SMI_STS[%d] occurred, but no "
"handler available.\n", i);
}
}
diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c
index 4feb502819..5057cdeb23 100644
--- a/src/soc/intel/fsp_baytrail/spi.c
+++ b/src/soc/intel/fsp_baytrail/spi.c
@@ -562,7 +562,7 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
/*
* This is a 'no data' command (like Write Enable), its
- * bitesout size was 1, decremented to zero while executing
+ * bytesout size was 1, decremented to zero while executing
* spi_setup_opcode() above. Tell the chip to send the
* command.
*/