tegra124: implement platform_prog_run()

The tegra124 SoC is currently booting up on the AVP cpu which
bootstraps the rest of the SoC. Upon exiting bootblock it
runs romstage from its faster armv7 core. Instead of hard
coding the stage loading operations use run_romstage().

Change-Id: Idddcfd5443f08d4dd41e1d9b71650ff6d4b14bc4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8847
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>

1 files changed, 21 insertions, 18 deletions

diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c
index f08ca413ad..1ccc394be2 100644
--- a/src/soc/nvidia/tegra124/bootblock.c
+++ b/src/soc/nvidia/tegra124/bootblock.c
@@ -22,16 +22,30 @@
 #include <bootblock_common.h>
 #include <cbfs.h>
 #include <console/console.h>
+#include <program_loading.h>
 #include <soc/clock.h>
 #include <soc/nvidia/tegra/apbmisc.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include "pinmux.h"
 #include "power.h"
 
-void main(void)
+static void run_next_stage(void *entry)
 {
-	void *entry;
+	ASSERT(entry);
+	clock_cpu0_config(entry);
+
+	power_enable_and_ungate_cpu();
+
+	/* Repair ram on cluster0 and cluster1 after CPU is powered on. */
+	ram_repair();
+
+	clock_cpu0_remove_reset();
 
+	clock_halt_avp();
+}
+
+void main(void)
+{
 	// enable pinmux clamp inputs
 	clamp_tristate_inputs();
 
@@ -70,21 +84,10 @@ void main(void)
 			  PINMUX_PWR_INT_N_FUNC_PMICINTR |
 			  PINMUX_INPUT_ENABLE);
 
-	if (IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE))
-		entry = NULL;
-	else
-		entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
-					CONFIG_CBFS_PREFIX "/romstage");
-
-	ASSERT(entry);
-	clock_cpu0_config(entry);
-
-	power_enable_and_ungate_cpu();
-
-	/* Repair ram on cluster0 and cluster1 after CPU is powered on. */
-	ram_repair();
-
-	clock_cpu0_remove_reset();
+	run_romstage();
+}
 
-	clock_halt_avp();
+void platform_prog_run(struct prog *prog)
+{
+	run_next_stage(prog_entry(prog));
 }