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authorMichał Żygowski <michal.zygowski@3mdeb.com>2020-03-20 16:19:55 +0100
committerMichał Żygowski <michal.zygowski@3mdeb.com>2020-03-25 08:05:43 +0000
commit8e46d42009f8d8f24787fcaa9785d62ae9260786 (patch)
tree50fc8758fa3bdfc31c0d18bf219dfcc2ce6eac88 /src
parentc04871a398ca945b42fde0867572094c38f6f92c (diff)
downloadcoreboot-8e46d42009f8d8f24787fcaa9785d62ae9260786.tar.xz
mb/pcengines/apu2: enable PCIe power management features
Enable ASPM L0s and L1, Common Clock and Clock Power Management for all PCIe ports. TEST=boot Debian linux and check new PCIe capabilities appear in lspci Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I0a4c83731742f31ab8ef1d326e800dfdc2abb1b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/pcengines/apu2/Kconfig4
-rw-r--r--src/mainboard/pcengines/apu2/OemCustomize.c20
2 files changed, 19 insertions, 5 deletions
diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig
index b434ddc810..1915cc22d7 100644
--- a/src/mainboard/pcengines/apu2/Kconfig
+++ b/src/mainboard/pcengines/apu2/Kconfig
@@ -30,6 +30,10 @@ config BOARD_SPECIFIC_OPTIONS
select GENERIC_SPD_BIN
select MAINBOARD_HAS_LPC_TPM
select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS
+ select PCIEXP_ASPM
+ select PCIEXP_CLK_PM
+ select PCIEXP_COMMON_CLOCK
+ select PCIEXP_L1_SUB_STATE
config MAINBOARD_DIR
string
diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c
index 6339e0fc4a..e47a2c8317 100644
--- a/src/mainboard/pcengines/apu2/OemCustomize.c
+++ b/src/mainboard/pcengines/apu2/OemCustomize.c
@@ -33,7 +33,9 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
- AspmDisabled, PCIE_PORT3_RESET_ID, 0)
+ AspmL0sL1,
+ PCIE_PORT3_RESET_ID,
+ ClkPmSupportEnabled)
},
/* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
{
@@ -43,7 +45,9 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
- AspmDisabled, PCIE_NIC_RESET_ID, 0)
+ AspmL0sL1,
+ PCIE_NIC_RESET_ID,
+ ClkPmSupportEnabled)
},
/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
{
@@ -53,7 +57,9 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
- AspmDisabled, PCIE_NIC_RESET_ID, 0)
+ AspmL0sL1,
+ PCIE_NIC_RESET_ID,
+ ClkPmSupportEnabled)
},
/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
{
@@ -63,7 +69,9 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
- AspmDisabled, PCIE_NIC_RESET_ID, 0)
+ AspmL0sL1,
+ PCIE_NIC_RESET_ID,
+ ClkPmSupportEnabled)
},
/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
{
@@ -73,7 +81,9 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
- AspmDisabled, PCIE_GFX_RESET_ID, 0)
+ AspmL0sL1,
+ PCIE_GFX_RESET_ID,
+ ClkPmSupportEnabled)
}
};