southbridge/via/vt8237r/acpi: Add IRQ routing

Includes objects for interrupt links, the LPC bridge and interrupt
routing tables for the internal devices for both APIC and legacy
modes.

The default routing tables only includes peripherals internal to the
VT8237R, if a mainboard has PCI slots (mine does not have), it needs to
supply its own routing table.

Change-Id: I3a0cdafc19159fe6c38e4dde08ad0bf2bd0dd6b8
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/18897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

3 files changed, 201 insertions, 0 deletions

diff --git a/src/southbridge/via/vt8237r/acpi/default_irq_route.asl b/src/southbridge/via/vt8237r/acpi/default_irq_route.asl
new file mode 100644
index 0000000000..2e9e76391a
--- /dev/null
+++ b/src/southbridge/via/vt8237r/acpi/default_irq_route.asl
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Lubomir Rintel <lkundrak@v3.sk>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+Method (_PRT, 0) {
+	If (LEqual (^ISAC.APIC, Zero)) {
+		Return (Package (20) {
+			/* AGP bridge */
+			Package (4) { 0x0001ffff, 0, ^ISAC.LNKA, 0x00 },
+			Package (4) { 0x0001ffff, 1, ^ISAC.LNKB, 0x00 },
+			Package (4) { 0x0001ffff, 2, ^ISAC.LNKC, 0x00 },
+			Package (4) { 0x0001ffff, 3, ^ISAC.LNKD, 0x00 },
+
+			/* IDE interface */
+			Package (4) { 0x000fffff, 0, ^ISAC.LNKA, 0x00 },
+			Package (4) { 0x000fffff, 1, ^ISAC.LNKB, 0x00 },
+			Package (4) { 0x000fffff, 2, ^ISAC.LNKC, 0x00 },
+			Package (4) { 0x000fffff, 3, ^ISAC.LNKD, 0x00 },
+
+			/* USB controller */
+			Package (4) { 0x0010ffff, 0, ^ISAC.LNKA, 0x00 },
+			Package (4) { 0x0010ffff, 1, ^ISAC.LNKB, 0x00 },
+			Package (4) { 0x0010ffff, 2, ^ISAC.LNKC, 0x00 },
+			Package (4) { 0x0010ffff, 3, ^ISAC.LNKD, 0x00 },
+
+			/* Audio (& LPC bridge) */
+			Package (4) { 0x0011ffff, 0, ^ISAC.LNKA, 0x00 },
+			Package (4) { 0x0011ffff, 1, ^ISAC.LNKB, 0x00 },
+			Package (4) { 0x0011ffff, 2, ^ISAC.LNKC, 0x00 },
+			Package (4) { 0x0011ffff, 3, ^ISAC.LNKD, 0x00 },
+
+			/* Ethernet controller */
+			Package (4) { 0x0012ffff, 0, ^ISAC.LNKA, 0x00 },
+			Package (4) { 0x0012ffff, 1, ^ISAC.LNKB, 0x00 },
+			Package (4) { 0x0012ffff, 2, ^ISAC.LNKC, 0x00 },
+			Package (4) { 0x0012ffff, 3, ^ISAC.LNKD, 0x00 }
+		})
+	} Else {
+		/* "Table 9. APIC Fixed IRQ Routing
+		 * When the internal APIC is enabled, internal IRQ
+		 * routing to the APIC is fixed as follows:" */
+		Return (Package (20) {
+			/* The graphics controller behind the AGP bridge */
+			/* INTA# => IRQ16 INTB# => IRQ17 INTC# => IRQ18 INTD# => IRQ19 */
+			Package (4) { 0x0001ffff, 0, 0x00, 16 },
+			Package (4) { 0x0001ffff, 1, 0x00, 17 },
+			Package (4) { 0x0001ffff, 2, 0x00, 18 },
+			Package (4) { 0x0001ffff, 3, 0x00, 19 },
+
+			/* IDE (Native Mode)/SATA IRQ & INTE => IRQ20 */
+			Package (4) { 0x000fffff, 0, 0x00, 20 },
+			Package (4) { 0x000fffff, 1, 0x00, 20 },
+			Package (4) { 0x000fffff, 2, 0x00, 20 },
+			Package (4) { 0x000fffff, 3, 0x00, 20 },
+
+			/* USB IRQ (all 5 functions) and INTF => IRQ21 */
+			Package (4) { 0x0010ffff, 0, 0x00, 21 },
+			Package (4) { 0x0010ffff, 1, 0x00, 21 },
+			Package (4) { 0x0010ffff, 2, 0x00, 21 },
+			Package (4) { 0x0010ffff, 3, 0x00, 21 },
+
+			/* AC’97 / MC’97 IRQ and INTG => IRQ22 */
+			Package (4) { 0x0011ffff, 0, 0x00, 22 },
+			Package (4) { 0x0011ffff, 1, 0x00, 22 },
+			Package (4) { 0x0011ffff, 2, 0x00, 22 },
+			Package (4) { 0x0011ffff, 3, 0x00, 22 },
+
+			/* LAN IRQ and INTH => IRQ23 */
+			Package (4) { 0x0012ffff, 0, 0x00, 23 },
+			Package (4) { 0x0012ffff, 1, 0x00, 23 },
+			Package (4) { 0x0012ffff, 2, 0x00, 23 },
+			Package (4) { 0x0012ffff, 3, 0x00, 23 }
+		})
+
+	}
+}
diff --git a/src/southbridge/via/vt8237r/acpi/irqlinks.asl b/src/southbridge/via/vt8237r/acpi/irqlinks.asl
new file mode 100644
index 0000000000..6c4c89a77f
--- /dev/null
+++ b/src/southbridge/via/vt8237r/acpi/irqlinks.asl
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Lubomir Rintel <lkundrak@v3.sk>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/x86/acpi/statdef.asl>
+
+/* Possible PNP IRQs */
+Name (PIRQ, ResourceTemplate () {
+	IRQ (Level, ActiveLow, Shared) {3, 4, 6, 7, 10, 11, 12}
+})
+
+#define IRQ_LINK(reg)						\
+	Name (_HID, EisaId ("PNP0C0F"))				\
+	Name (_UID, 1)						\
+								\
+	Method (_STA, 0) {					\
+		If (LEqual (reg, 0x00)) {			\
+			Return (STA_DISABLED)			\
+		}						\
+		Return (STA_INVISIBLE)				\
+	}							\
+								\
+	Method (_PRS, 0) {					\
+		Return (PIRQ)					\
+	}							\
+								\
+	Name (CRSA, ResourceTemplate () {			\
+		IRQ (Level, ActiveLow, Shared) {}		\
+	})							\
+	Method (_CRS, 0) {					\
+		CreateWordField (CRSA, 0x1, AINT)		\
+		ShiftLeft (One, reg, AINT)			\
+		Return (CRSA)					\
+	}							\
+								\
+	Method (_SRS, 1) {					\
+		CreateWordField (Arg0, 0x1, AINT)		\
+		Store (Zero, Local0)				\
+		Store (AINT, Local1)				\
+		While (LNotEqual (Local1, One)) {		\
+			ShiftRight (Local1, One, Local1)	\
+			Increment (Local0)			\
+		}						\
+		Store (Local0, reg)				\
+	}							\
+								\
+	Method (_DIS, 0) {					\
+		Store (Zero, reg)				\
+	}							\
+
+Device (LNKA) { IRQ_LINK (INTA) }
+Device (LNKB) { IRQ_LINK (INTB) }
+Device (LNKC) { IRQ_LINK (INTC) }
+Device (LNKD) { IRQ_LINK (INTD) }
diff --git a/src/southbridge/via/vt8237r/acpi/lpc.asl b/src/southbridge/via/vt8237r/acpi/lpc.asl
new file mode 100644
index 0000000000..f13a96bb29
--- /dev/null
+++ b/src/southbridge/via/vt8237r/acpi/lpc.asl
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Lubomir Rintel <lkundrak@v3.sk>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* VT8237 ISA bridge */
+Device (ISAC)
+{
+	Name (_ADR, 0x00110000)
+
+	OperationRegion (ISAB, PCI_Config, 0x00, 0xEF)
+	Field (ISAB, DWordAcc, NoLock, Preserve) {
+
+		/* PCI PNP Interrupt Routing 1 */
+		Offset (0x55),
+		    , 4,	/* Reserved */
+		INTA, 4,	/* PCI INTA# Routing */
+
+		/* PCI PNP Interrupt Routing 2 */
+		Offset (0x56),
+		INTB, 4,	/* PCI INTB# Routing */
+		INTC, 4,	/* PCI INTC# Routing */
+
+		/* PCI PNP Interrupt Routing 3 */
+		Offset (0x57),
+		    , 4,	/* Reserved */
+		INTD, 4,	/* PCI INTD# Routing */
+
+		/* Miscellaneous Control 0 */
+		Offset (0x58),
+		    , 6,
+		APIC, 1,	/* Internal APIC Enable */
+	}
+
+	#include "irqlinks.asl"
+}