diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-12-16 05:46:16 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-12-17 18:13:38 +0000 |
| commit | 9612a3c32a95791c1084ade5ae89e9147b2c2b7b (patch) | |
| tree | 7094c29ddd82729151c048b45c8f6ca022114fe6 /src | |
| parent | 555efe47922c8b347ad7cd2c9759740e3e228164 (diff) | |
| download | coreboot-9612a3c32a95791c1084ade5ae89e9147b2c2b7b.tar.xz | |
cpu/intel: Remove ROMCC header guards and code
Intel's platforms use a GCC compiled bootblock.
Change-Id: I779d7115fee75df9356873e9cc66d43280821812
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/intel/car/non-evict/cache_as_ram.S | 3 | ||||
| -rw-r--r-- | src/cpu/intel/car/romstage.c | 13 | ||||
| -rw-r--r-- | src/cpu/intel/microcode/Kconfig | 2 | ||||
| -rw-r--r-- | src/cpu/intel/microcode/microcode.c | 18 |
4 files changed, 2 insertions, 34 deletions
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 5a668c42df..4dee0a8002 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -28,11 +28,8 @@ _cache_as_ram_setup: bootblock_pre_c_entry: - -#if !CONFIG(ROMCC_BOOTBLOCK) movl $cache_as_ram, %esp /* return address */ jmp check_mtrr /* Check if CPU properly reset */ -#endif cache_as_ram: post_code(0x20) diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 1f8eb9a10e..bd6a5a9b8c 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -71,19 +71,6 @@ static void romstage_main(unsigned long bist) /* We do not return here. */ } -#if CONFIG(ROMCC_BOOTBLOCK) -/* This wrapper enables easy transition away from ROMCC_BOOTBLOCK - * keeping changes in cache_as_ram.S easy to manage. - */ -asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) -{ - timestamp_init(base_timestamp); - timestamp_add_now(TS_START_ROMSTAGE); - romstage_main(bist); -} -#endif - - /* We don't carry BIST from bootblock in a good location to read from. * Any error should have been reported in bootblock already. */ diff --git a/src/cpu/intel/microcode/Kconfig b/src/cpu/intel/microcode/Kconfig index 73afe0bb45..238aad745d 100644 --- a/src/cpu/intel/microcode/Kconfig +++ b/src/cpu/intel/microcode/Kconfig @@ -1,7 +1,7 @@ config MICROCODE_UPDATE_PRE_RAM bool depends on SUPPORT_CPU_UCODE_IN_CBFS - default y if !ROMCC_BOOTBLOCK + default y help Select this option if you want to update the microcode during the cache as ram setup. diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 80470bf236..90138be236 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -15,11 +15,7 @@ #include <stdint.h> #include <stddef.h> -#if !defined(__ROMCC__) #include <cbfs.h> -#else -#include <arch/cbfs.h> -#endif #include <arch/cpu.h> #include <console/console.h> #include <cpu/x86/msr.h> @@ -141,22 +137,11 @@ const void *intel_microcode_find(void) unsigned int x86_model, x86_family; msr_t msr; -#ifdef __ROMCC__ - struct cbfs_file *microcode_file; - - microcode_file = walkcbfs_head((char *) MICROCODE_CBFS_FILE); - if (!microcode_file) - return NULL; - - ucode_updates = CBFS_SUBHEADER(microcode_file); - microcode_len = ntohl(microcode_file->len); -#else ucode_updates = cbfs_boot_map_with_leak(MICROCODE_CBFS_FILE, CBFS_TYPE_MICROCODE, µcode_len); if (ucode_updates == NULL) return NULL; -#endif /* CPUID sets MSR 0x8B if a microcode update has been loaded. */ msr.lo = 0; @@ -201,8 +186,7 @@ const void *intel_microcode_find(void) microcode_len -= update_size; } - /* ROMCC doesn't like NULL. */ - return (void *)0; + return NULL; } void intel_update_microcode_from_cbfs(void) |