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| author | Aamir Bohra <aamir.bohra@intel.com> | 2020-05-18 11:00:04 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-20 09:11:40 +0000 |
| commit | a2789328f77c5b47006f4a48f59f278e699821dc (patch) | |
| tree | 4fd0f80575b030ac3f2dd2ed046cda9411d09eaf /src | |
| parent | 8952de55cb4949969b09219fdf6b9b14f3b59b0c (diff) | |
| download | coreboot-a2789328f77c5b47006f4a48f59f278e699821dc.tar.xz | |
soc/intel/common/acpi: Remove gpio community range
Remove hardcoded gpio community range, since it might differ across
the SOCs.
Change-Id: I79c10669f6096537d466d1abd356d58a50fcb8f5
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/common/acpi/gpio.asl | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/common/acpi/gpio.asl b/src/soc/intel/common/acpi/gpio.asl index cac3449352..dbfa7af980 100644 --- a/src/soc/intel/common/acpi/gpio.asl +++ b/src/soc/intel/common/acpi/gpio.asl @@ -3,7 +3,7 @@ /* * Configure GPIO Power Management bits * - * Arg0: GPIO community (0-5) + * Arg0: GPIO community index * Arg1: PM bits in MISCCFG */ Method (CGPM, 2, Serialized) |