diff options
| author | Youness Alaoui <kakaroto@kakaroto.homelinux.net> | 2017-02-07 13:59:29 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-02-22 22:25:24 +0100 |
| commit | a462c157f8a98e9e115e84a2d9d142c9b878210e (patch) | |
| tree | 6e1b07f876696251e000e4bf4074ad8ea794558a /src | |
| parent | 696ebc2dbc64c3a76b45080cebf9949db00348e2 (diff) | |
| download | coreboot-a462c157f8a98e9e115e84a2d9d142c9b878210e.tar.xz | |
purism/librem13: Fix M.2 issues.
The M.2 SSD is on the SATA port 3, which also required the DTLE setting
to be set.
This fixes issues with the M.2 SSD not being detected/stable.
Change-Id: Id39d9ec395a2d9d32be4c079678d0708f08b3935
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/18409
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/purism/librem13/devicetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/purism/librem13/devicetree.cb b/src/mainboard/purism/librem13/devicetree.cb index 6bc55214d5..072e2129fb 100644 --- a/src/mainboard/purism/librem13/devicetree.cb +++ b/src/mainboard/purism/librem13/devicetree.cb @@ -24,6 +24,7 @@ chip soc/intel/broadwell # Port 0 tuning for link stability register "sata_port0_gen3_dtle" = "9" + register "sata_port3_gen3_dtle" = "9" device cpu_cluster 0 on device lapic 0 on end |