diff options
| author | Ionela Voinescu <ionela.voinescu@imgtec.com> | 2015-02-02 14:34:24 +0000 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-14 12:08:28 +0200 |
| commit | a7023904e653a0ae869d53d9fad8a56baab2d94a (patch) | |
| tree | 2b1519e0f60a295838e35c6acb06a98fa985e630 /src | |
| parent | 8b1f23ef0307974737f49b237664f66f5e2c35c7 (diff) | |
| download | coreboot-a7023904e653a0ae869d53d9fad8a56baab2d94a.tar.xz | |
pistachio: Fix ROM clock base address
The base address used was TOP CLOCK control address instead of
the PERIPH CLOCK CONTROL. That was incorrect and is fixed with
the current patch.
BUG=chrome-os-partner:31438
TEST=tested on Pistachio bring up board; now the hash accelerator,
fed by this clock, is correctly clocked at 200MHz.
BRANCH=none
Change-Id: I0ead3951dc1dfc872881b8d1ae9b63f8104af50d
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 871cb50ca43a6c760f346eb447e8ff102d8ca0b6
Original-Change-Id: I198d64f97a85a6fcf00c3853bf23d2d767e0e631
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/245313
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9670
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/imgtec/pistachio/clocks.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/imgtec/pistachio/clocks.c b/src/soc/imgtec/pistachio/clocks.c index d50abf578d..5b226407c7 100644 --- a/src/soc/imgtec/pistachio/clocks.c +++ b/src/soc/imgtec/pistachio/clocks.c @@ -99,7 +99,7 @@ #define UART1CLKOUT_MASK 0x000003FF /* Definitions for ROM clock setup */ -#define ROMCLKOUT_CTRL_ADDR 0xB814410C +#define ROMCLKOUT_CTRL_ADDR 0xB814490C #define ROMCLKOUT_MASK 0x0000007F /* Definitions for ETH clock setup */ |