sb/common/intel/spi.c: Don't use typedefs for structs

Change-Id: Id0ed621b5b4b5634d454811b1e1beeb27fc69ea8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

1 files changed, 28 insertions, 30 deletions

diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index bf2a44c86c..5a4b26fa66 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -38,11 +38,9 @@
 
 static int spi_is_multichip(void);
 
-typedef struct spi_slave ich_spi_slave;
-
 static int g_ichspi_lock = 0;
 
-typedef struct ich7_spi_regs {
+struct ich7_spi_regs {
 	uint16_t spis;
 	uint16_t spic;
 	uint32_t spia;
@@ -53,9 +51,9 @@ typedef struct ich7_spi_regs {
 	uint16_t optype;
 	uint8_t opmenu[8];
 	uint32_t pbr[3];
-} __packed ich7_spi_regs;
+} __packed;
 
-typedef struct ich9_spi_regs {
+struct ich9_spi_regs {
 	uint32_t bfpr;
 	uint16_t hsfs;
 	uint16_t hsfc;
@@ -86,15 +84,15 @@ typedef struct ich9_spi_regs {
 	uint32_t srdl;
 	uint32_t srdc;
 	uint32_t srd;
-} __packed ich9_spi_regs;
+} __packed;
 
-typedef struct ich_spi_controller {
+struct ich_spi_controller {
 	int locked;
 	uint32_t flmap0;
 	uint32_t flcomp;
 	uint32_t hsfs;
 
-	ich9_spi_regs *ich9_spi;
+	struct ich9_spi_regs *ich9_spi;
 	uint8_t *opmenu;
 	int menubytes;
 	uint16_t *preop;
@@ -107,9 +105,9 @@ typedef struct ich_spi_controller {
 	uint32_t *bbar;
 	uint32_t *fpr;
 	uint8_t fpr_max;
-} ich_spi_controller;
+};
 
-static ich_spi_controller g_cntlr;
+static struct ich_spi_controller g_cntlr;
 
 enum {
 	SPIS_SCIP =		0x0001,
@@ -254,7 +252,7 @@ static void read_reg(const void *src, void *value, uint32_t size)
 
 static void ich_set_bbar(uint32_t minaddr)
 {
-	ich_spi_controller *cntlr = &g_cntlr;
+	struct ich_spi_controller *cntlr = &g_cntlr;
 	const uint32_t bbar_mask = 0x00ffff00;
 	uint32_t ichspi_bbar;
 
@@ -266,12 +264,12 @@ static void ich_set_bbar(uint32_t minaddr)
 
 void spi_init(void)
 {
-	ich_spi_controller *cntlr = &g_cntlr;
+	struct ich_spi_controller *cntlr = &g_cntlr;
 	uint8_t *rcrb; /* Root Complex Register Block */
 	uint32_t rcba; /* Root Complex Base Address */
 	uint8_t bios_cntl;
-	ich9_spi_regs *ich9_spi;
-	ich7_spi_regs *ich7_spi;
+	struct ich9_spi_regs *ich9_spi;
+	struct ich7_spi_regs *ich7_spi;
 	uint16_t hsfs;
 
 #ifdef __SIMPLE_DEVICE__
@@ -284,7 +282,7 @@ void spi_init(void)
 	/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
 	rcrb = (uint8_t *)(rcba & 0xffffc000);
 	if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) {
-		ich7_spi = (ich7_spi_regs *)(rcrb + 0x3020);
+		ich7_spi = (struct ich7_spi_regs *)(rcrb + 0x3020);
 		cntlr->opmenu = ich7_spi->opmenu;
 		cntlr->menubytes = sizeof(ich7_spi->opmenu);
 		cntlr->optype = &ich7_spi->optype;
@@ -299,7 +297,7 @@ void spi_init(void)
 		cntlr->fpr = &ich7_spi->pbr[0];
 		cntlr->fpr_max = 3;
 	} else {
-		ich9_spi = (ich9_spi_regs *)(rcrb + 0x3800);
+		ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800);
 		cntlr->ich9_spi = ich9_spi;
 		hsfs = readw_(&ich9_spi->hsfs);
 		g_ichspi_lock = hsfs & HSFS_FLOCKDN;
@@ -399,7 +397,7 @@ static void spi_setup_type(spi_transaction *trans)
 
 static int spi_setup_opcode(spi_transaction *trans)
 {
-	ich_spi_controller *cntlr = &g_cntlr;
+	struct ich_spi_controller *cntlr = &g_cntlr;
 	uint16_t optypes;
 	uint8_t opmenu[cntlr->menubytes];
 
@@ -480,7 +478,7 @@ static int spi_setup_offset(spi_transaction *trans)
  */
 static int ich_status_poll(u16 bitmask, int wait_til_set)
 {
-	ich_spi_controller *cntlr = &g_cntlr;
+	struct ich_spi_controller *cntlr = &g_cntlr;
 	int timeout = 600000; /* This will result in 6 seconds */
 	u16 status = 0;
 
@@ -501,7 +499,7 @@ static int ich_status_poll(u16 bitmask, int wait_til_set)
 
 static int spi_is_multichip(void)
 {
-	ich_spi_controller *cntlr = &g_cntlr;
+	struct ich_spi_controller *cntlr = &g_cntlr;
 	if (!(cntlr->hsfs & HSFS_FDV))
 		return 0;
 	return !!((cntlr->flmap0 >> 8) & 3);
@@ -510,7 +508,7 @@ static int spi_is_multichip(void)
 static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
 		size_t bytesout, void *din, size_t bytesin)
 {
-	ich_spi_controller *cntlr = &g_cntlr;
+	struct ich_spi_controller *cntlr = &g_cntlr;
 	uint16_t control;
 	int16_t opcode_index;
 	int with_address;
@@ -660,7 +658,7 @@ spi_xfer_exit:
 /* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */
 static void ich_hwseq_set_addr(uint32_t addr)
 {
-	ich_spi_controller *cntlr = &g_cntlr;
+	struct ich_spi_controller *cntlr = &g_cntlr;
 	uint32_t addr_old = readl_(&cntlr->ich9_spi->faddr) & ~0x01FFFFFF;
 
 	writel_((addr & 0x01FFFFFF) | addr_old, &cntlr->ich9_spi->faddr);
@@ -673,7 +671,7 @@ static void ich_hwseq_set_addr(uint32_t addr)
 static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
 					     unsigned int len)
 {
-	ich_spi_controller *cntlr = &g_cntlr;
+	struct ich_spi_controller *cntlr = &g_cntlr;
 	uint16_t hsfs;
 	uint32_t addr;
 
@@ -713,7 +711,7 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
 static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset,
 			size_t len)
 {
-	ich_spi_controller *cntlr = &g_cntlr;
+	struct ich_spi_controller *cntlr = &g_cntlr;
 	u32 start, end, erase_size;
 	int ret;
 	uint16_t hsfc;
@@ -763,7 +761,7 @@ out:
 
 static void ich_read_data(uint8_t *data, int len)
 {
-	ich_spi_controller *cntlr = &g_cntlr;
+	struct ich_spi_controller *cntlr = &g_cntlr;
 	int i;
 	uint32_t temp32 = 0;
 
@@ -778,7 +776,7 @@ static void ich_read_data(uint8_t *data, int len)
 static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len,
 			void *buf)
 {
-	ich_spi_controller *cntlr = &g_cntlr;
+	struct ich_spi_controller *cntlr = &g_cntlr;
 	uint16_t hsfc;
 	uint16_t timeout = 100 * 60;
 	uint8_t block_len;
@@ -824,7 +822,7 @@ static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len,
  */
 static void ich_fill_data(const uint8_t *data, int len)
 {
-	ich_spi_controller *cntlr = &g_cntlr;
+	struct ich_spi_controller *cntlr = &g_cntlr;
 	uint32_t temp32 = 0;
 	int i;
 
@@ -848,7 +846,7 @@ static void ich_fill_data(const uint8_t *data, int len)
 static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len,
 			const void *buf)
 {
-	ich_spi_controller *cntlr = &g_cntlr;
+	struct ich_spi_controller *cntlr = &g_cntlr;
 	uint16_t hsfc;
 	uint16_t timeout = 100 * 60;
 	uint8_t block_len;
@@ -904,7 +902,7 @@ static const struct spi_flash_ops spi_flash_ops = {
 static int spi_flash_programmer_probe(const struct spi_slave *spi,
 					struct spi_flash *flash)
 {
-	ich_spi_controller *cntlr = &g_cntlr;
+	struct ich_spi_controller *cntlr = &g_cntlr;
 
 	if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX))
 		return spi_flash_generic_probe(spi, flash);
@@ -984,7 +982,7 @@ static int spi_flash_protect(const struct spi_flash *flash,
 			const struct region *region,
 			const enum ctrlr_prot_type type)
 {
-	ich_spi_controller *cntlr = &g_cntlr;
+	struct ich_spi_controller *cntlr = &g_cntlr;
 	u32 start = region_offset(region);
 	u32 end = start + region_sz(region) - 1;
 	u32 reg;
@@ -1043,7 +1041,7 @@ static int spi_flash_protect(const struct spi_flash *flash,
 
 static const struct spi_ctrlr spi_ctrlr = {
 	.xfer_vector = xfer_vectors,
-	.max_xfer_size = member_size(ich9_spi_regs, fdata),
+	.max_xfer_size = member_size(struct ich9_spi_regs, fdata),
 	.flash_probe = spi_flash_programmer_probe,
 	.flash_protect = spi_flash_protect,
 };