diff options
| author | Nick Vaccaro <nvaccaro@google.com> | 2018-05-16 02:52:28 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-05-23 08:18:54 +0000 |
| commit | ba959ad2db9d9f31b7401e89d9c2ede147bb5a22 (patch) | |
| tree | 1721e0067a3e8be4db570f8aeb839c55c19a6891 /src | |
| parent | 8c4b526fd212389f065ef96ec034ba0c3f088252 (diff) | |
| download | coreboot-ba959ad2db9d9f31b7401e89d9c2ede147bb5a22.tar.xz | |
mb/google/poppy/variants/nocturne: enable I2C #5 bus
Enable I2C #5 for rear camera and SAR.
BUG=b:79784124
BRANCH=none
TEST='emerge-nocturne coreboot chromeos-bootimage' and verify i2c bus #5
is detected.
Change-Id: Ic5b754fb97231aeab0278d71f8ced9343c30feda
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/26319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/poppy/variants/nocturne/devicetree.cb | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 6feb337536..621bbe495d 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -197,7 +197,7 @@ chip soc/intel/skylake }, }" - # Camera + # Front Camera register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8" register "i2c[3]" = "{ .speed = I2C_SPEED_FAST, @@ -217,6 +217,14 @@ chip soc/intel/skylake } }" + # Rear Camera & SAR + register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" + register "i2c[5]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 98, + .fall_time_ns = 38, + }" + # GSPI0 for cr50 TPM register "gspi[0]" = "{ .speed_mhz = 1, @@ -229,7 +237,7 @@ chip soc/intel/skylake [PchSerialIoIndexI2C2] = PchSerialIoDisabled, [PchSerialIoIndexI2C3] = PchSerialIoPci, [PchSerialIoIndexI2C4] = PchSerialIoPci, - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, [PchSerialIoIndexSpi0] = PchSerialIoPci, [PchSerialIoIndexSpi1] = PchSerialIoPci, [PchSerialIoIndexUart0] = PchSerialIoSkipInit, @@ -272,7 +280,7 @@ chip soc/intel/skylake device pci 16.4 off end # Management Engine Interface 3 device pci 17.0 off end # SATA device pci 19.0 on end # UART #2 - device pci 19.1 off end # I2C #5 + device pci 19.1 on end # I2C #5 device pci 19.2 on chip drivers/i2c/max98373 register "vmon_slot_no" = "4" |