diff options
| author | Li-Ta Lo <ollie@lanl.gov> | 2006-02-28 15:39:25 +0000 |
|---|---|---|
| committer | Li-Ta Lo <ollie@lanl.gov> | 2006-02-28 15:39:25 +0000 |
| commit | bab9446dfd715255d7c8dbefa11a214ffc354cab (patch) | |
| tree | 224e9ec0007e7d3ca2e677742629642acca1c6fb /src | |
| parent | a51e6f1e560a1dc40ec0c9522733d5f8422f041f (diff) | |
| download | coreboot-bab9446dfd715255d7c8dbefa11a214ffc354cab.tar.xz | |
semi working with random 1 bit error
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2186 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/amd/rumba/auto.c | 34 | ||||
| -rw-r--r-- | src/northbridge/amd/gx2/raminit.c | 24 |
2 files changed, 44 insertions, 14 deletions
diff --git a/src/mainboard/amd/rumba/auto.c b/src/mainboard/amd/rumba/auto.c index b15937126b..08fe8ed6ca 100644 --- a/src/mainboard/amd/rumba/auto.c +++ b/src/mainboard/amd/rumba/auto.c @@ -60,8 +60,36 @@ static void msr_init(void) } -static pll_reset(void) +static void pll_reset(void) { + msr_t msr; + + msr = rdmsr(0x4c000014); + print_debug("CGLP_SYS_RSTPLL "); + print_debug_hex32(msr.hi); + print_debug(":"); + print_debug_hex32(msr.lo); + print_debug("\n\r"); + + if ((msr.lo >> 26) & 0x3F) { + print_debug("reboot from BIOS reset\n\r"); + return; + } + print_debug("prgramming PLL\n\r"); + + msr.hi = 0x00000019; + msr.lo = 0x06de0378; + wrmsr(0x4c000014, msr); + msr.lo |= ((0xde << 16) | (1 << 26)); + wrmsr(0x4c000014, msr); + + print_debug("Reset PLL\n\r"); + + msr.lo |= ((1<<14) |(1<<13) | (1<<0)); + wrmsr(0x4c000014,msr); + + print_debug("should not be here\n\r"); + } static void main(unsigned long bist) @@ -76,7 +104,9 @@ static void main(unsigned long bist) uart_init(); console_init(); - print_err("hi\n"); + print_err("hi\n\r"); + + pll_reset(); /* Halt if there was a built in self test failure */ //report_bist_failure(bist); diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c index 1b2ad6a6b9..2ad46b6170 100644 --- a/src/northbridge/amd/gx2/raminit.c +++ b/src/northbridge/amd/gx2/raminit.c @@ -48,15 +48,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) wrmsr(0x2000201d, msr); print_debug("sdram_enable step 3\r\n"); - /* 4. set and clear REF_TST 16 times, more shouldn't hurt */ - for (i = 0; i < 19; i++) { - msr = rdmsr(0x20000018); - msr.lo |= (0x01 << 3); - wrmsr(0x20000018, msr); - msr.lo &= !(0x01 << 3); - wrmsr(0x20000018, msr); - } - print_debug("sdram_enable step 4\r\n"); /* 5. set refresh interval */ msr = rdmsr(0x20000018); @@ -68,7 +59,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) msr.lo &= !(0x03 << 6); wrmsr(0x20000018, msr); - /* 6. enable RLL, load Extended Mode Register by set and clear PROG_DRAM */ msr = rdmsr(0x20000018); msr.lo |= ((0x01 << 28) | 0x01); @@ -96,14 +86,24 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) wrmsr(0x20000018, msr); print_debug("sdram_enable step 10\r\n"); + /* 4. set and clear REF_TST 16 times, more shouldn't hurt */ + for (i = 0; i < 19; i++) { + msr = rdmsr(0x20000018); + msr.lo |= (0x01 << 3); + wrmsr(0x20000018, msr); + msr.lo &= !(0x01 << 3); + wrmsr(0x20000018, msr); + } + print_debug("sdram_enable step 4\r\n"); + /* wait 200 SDCLKs */ for (i = 0; i < 200; i++) outb(0xaa, 0x80); /* load RDSYNC */ - msr = rdmsr(0x2000001a); + msr = rdmsr(0x2000001f); msr.hi = 0x000ff310; - wrmsr(0x20000018, msr); + wrmsr(0x2000001f, msr); print_debug("sdram_enable step 10\r\n"); /* DRAM working now?? */ |