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| author | Aaron Durbin <adurbin@chromium.org> | 2016-11-18 08:10:35 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-11-19 16:55:52 +0100 |
| commit | bff8c5ec1977039b7edd1de02768c44a7055fce9 (patch) | |
| tree | a6afdabba2b71a3c0f1ff6d96f437e044661804c /src | |
| parent | e39a8a9c092ed66686632d591ec84ed7a6165a50 (diff) | |
| download | coreboot-bff8c5ec1977039b7edd1de02768c44a7055fce9.tar.xz | |
soc/intel/common/lpss_i2c: fix NULL dereference in error path
If the SoC clock speed is not supported there is supposed to
be an error printed. However, the value printed was wrong which
was dereferencing a NULL struct. Fix that.
Change-Id: I5021ad8c1581d1935b39875ffa3aa00b594c537a
Found-by: Coverity Scan #1365977
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17468
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/common/lpss_i2c.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/common/lpss_i2c.c b/src/soc/intel/common/lpss_i2c.c index 49fb85d6a6..025ee25f57 100644 --- a/src/soc/intel/common/lpss_i2c.c +++ b/src/soc/intel/common/lpss_i2c.c @@ -539,7 +539,7 @@ static int lpss_i2c_gen_config_rise_fall_time(struct lpss_i2c_regs *regs, if (soc == NULL) { printk(BIOS_ERR, "lpss_i2c: invalid SoC clock speed %d MHz\n", - soc->clk_speed_mhz); + ic_clk); return -1; } |