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authorAaron Durbin <adurbin@chromium.org>2016-07-14 00:26:50 -0500
committerAaron Durbin <adurbin@chromium.org>2016-07-15 08:35:49 +0200
commitc2b7779d60107a38f635980f74e39e5c68774bd2 (patch)
treeba936716ff583c288eb13527fb91d316f066fe64 /src
parent996b15c934df0777d396ed8792e77afccbd807e7 (diff)
downloadcoreboot-c2b7779d60107a38f635980f74e39e5c68774bd2.tar.xz
soc/intel/apollolake: provide poweroff() implementation
Implement poweroff() by putting the chipset into ACPI S5 state. BUG=chrome-os-partner:54977 Change-Id: I4ee269f03afd252d4bce909a8cc7c64d6270b16e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15686 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/apollolake/pmutil.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c
index 874d9ad60c..e23feb2109 100644
--- a/src/soc/intel/apollolake/pmutil.c
+++ b/src/soc/intel/apollolake/pmutil.c
@@ -21,6 +21,7 @@
#include <console/console.h>
#include <rules.h>
#include <device/pci_def.h>
+#include <halt.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
@@ -413,3 +414,9 @@ void vboot_platform_prepare_reboot(void)
const uint16_t port = ACPI_PMIO_BASE + PM1_CNT;
outl((inl(port) & ~(SLP_TYP)) | (SLP_TYP_S5 << SLP_TYP_SHIFT), port);
}
+
+void poweroff(void)
+{
+ enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
+ halt();
+}