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authorSubrata Banik <subrata.banik@intel.com>2017-02-27 12:21:49 +0530
committerAaron Durbin <adurbin@chromium.org>2017-03-06 20:40:15 +0100
commitc2c8397dbbe8bd36d2bc3c1a6a0960d574294585 (patch)
tree89671803ebe0e0be6e06cab79c077b391875a0f1 /src
parent79fc33ac7723809d11870b9276618ba29edb2f2b (diff)
downloadcoreboot-c2c8397dbbe8bd36d2bc3c1a6a0960d574294585.tar.xz
soc/intel/skylake: Clean up XHCI code
Don't need "skylake/include/soc/xhci.h", hence removed. Change-Id: I35df2003f311b557b622ce1d7a1c2e832693c2fc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18508 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/skylake/include/soc/xhci.h60
-rw-r--r--src/soc/intel/skylake/xhci.c1
2 files changed, 0 insertions, 61 deletions
diff --git a/src/soc/intel/skylake/include/soc/xhci.h b/src/soc/intel/skylake/include/soc/xhci.h
deleted file mode 100644
index c52022372b..0000000000
--- a/src/soc/intel/skylake/include/soc/xhci.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_XHCI_H_
-#define _SOC_XHCI_H_
-
-#include <rules.h>
-
-/* XHCI PCI Registers */
-#define XHCI_PWR_CTL_STS 0x74
-#define XHCI_PWR_CTL_SET_MASK 0x3
-#define XHCI_PWR_CTL_SET_D0 0x0
-#define XHCI_PWR_CTL_SET_D3 0x3
-#define XHCI_PWR_CTL_ENABLE_PME (1 << 8)
-#define XHCI_PWR_CTL_STATUS_PME (1 << 15)
-#define XHCI_USB2PR 0xd0
-#define XHCI_USB2PRM 0xd4
-#define XHCI_USB2PR_HCSEL 0x7fff
-#define XHCI_USB3PR 0xd8
-#define XHCI_USB3PR_SSEN 0x3f
-#define XHCI_USB3PRM 0xdc
-#define XHCI_USB3FUS 0xe0
-#define XHCI_USB3FUS_SS_MASK 3
-#define XHCI_USB3FUS_SS_SHIFT 3
-#define XHCI_USB3PDO 0xe8
-
-/* XHCI Memory Registers */
-#define XHCI_USB3_PORTSC(port) (0x510 + (port * 0x10))
-#define XHCI_USB3_PORTSC_CHST (0x7f << 17)
-#define XHCI_USB3_PORTSC_WCE (1 << 25) /* Wake on Connect */
-#define XHCI_USB3_PORTSC_WDE (1 << 26) /* Wake on Disconnect */
-#define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */
-#define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */
-#define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */
-#define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */
-#define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */
-#define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */
-#define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */
-#define XHCI_PLSR_RXDETECT (5 << 5) /* Port is disconnected */
-#define XHCI_PLSR_POLLING (7 << 5) /* Port is polling */
-#define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */
-
-#if ENV_SMM
-void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ);
-#endif
-
-#endif
diff --git a/src/soc/intel/skylake/xhci.c b/src/soc/intel/skylake/xhci.c
index 5ee34dfc68..0912f10a7e 100644
--- a/src/soc/intel/skylake/xhci.c
+++ b/src/soc/intel/skylake/xhci.c
@@ -21,7 +21,6 @@
#include <device/pci_ids.h>
#include <arch/io.h>
#include <soc/ramstage.h>
-#include <soc/xhci.h>
#include <soc/cpu.h>
static struct device_operations usb_xhci_ops = {