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| author | Ward Vandewege <ward@gnu.org> | 2008-04-23 00:40:39 +0000 |
|---|---|---|
| committer | Ward Vandewege <ward@gnu.org> | 2008-04-23 00:40:39 +0000 |
| commit | c4a4116440b4218ec1d3a93f9ce1ddda1ee5d4fe (patch) | |
| tree | a7a5ae1f8feb4cf3a21be41922e82276395c8028 /src | |
| parent | a74a8ffa0702a05eadf92605e77bc8c9a86b377a (diff) | |
| download | coreboot-c4a4116440b4218ec1d3a93f9ce1ddda1ee5d4fe.tar.xz | |
This patch fixes the 3 broken sata ports on the Tyan s2891 (primary port on
secondary controller was ok). There were two problems: the master sata
controller was not being initialized, and the irqs for the secondary ports on
both controllers were not being set in the mptable.
Thanks for Jonathan Kollasch for all the help figuring out the IRQ problem.
While all ports work reliably under a recent kernel (2.6.24), sata is about
half as fast as under the proprietary bios, according to bonnie++. That still
needs fixing...
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3253 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/tyan/s2891/mptable.c | 2 | ||||
| -rw-r--r-- | src/southbridge/nvidia/ck804/ck804_early_setup.c | 12 |
2 files changed, 13 insertions, 1 deletions
diff --git a/src/mainboard/tyan/s2891/mptable.c b/src/mainboard/tyan/s2891/mptable.c index b383aae2b7..75b9056bfe 100644 --- a/src/mainboard/tyan/s2891/mptable.c +++ b/src/mainboard/tyan/s2891/mptable.c @@ -79,7 +79,7 @@ void *smp_write_config_table(void *v) /* Initialize interrupt mapping*/ - dword = 0x0000d218; + dword = 0x0120d218; pci_write_config32(dev, 0x7c, dword); dword = 0x12008a00; diff --git a/src/southbridge/nvidia/ck804/ck804_early_setup.c b/src/southbridge/nvidia/ck804/ck804_early_setup.c index cf59d2f850..6eff2c624f 100644 --- a/src/southbridge/nvidia/ck804/ck804_early_setup.c +++ b/src/southbridge/nvidia/ck804/ck804_early_setup.c @@ -228,6 +228,18 @@ static void ck804_early_setup(void) RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, #endif + // Activate master port on primary SATA controller + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x50), ~(0x1f000013), 0x15000013, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x64), ~(0x00000001), 0x00000001, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x68), ~(0x02000000), 0x02000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x70), ~(0x000f0000), 0x00040000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xa0), ~(0x000001ff), 0x00000150, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x7c), ~(0x00000010), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xd0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xe0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013, RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001, RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000, |