diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-04-03 09:56:57 -0500 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-04-03 19:26:25 +0200 |
| commit | c6f27226a84434182771dbbcd593d223072801f7 (patch) | |
| tree | 589bd58ab19f04ac454d299549d18e15c5d87f0e /src | |
| parent | 23f50166c64be0c1d3656ca67839843bf11a5274 (diff) | |
| download | coreboot-c6f27226a84434182771dbbcd593d223072801f7.tar.xz | |
sandybridge: enable ROM caching
If ROM caching is selected the sandybridge chipset code will
will enable ROM caching after all other CPU threads are brought
up.
Change-Id: I3a57ba8753678146527ebf9547f5fbbd4f441f43
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3017
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/sandybridge/northbridge.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index c39933f1c1..b8022b8cea 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -25,6 +25,7 @@ #include <delay.h> #include <cpu/intel/model_206ax/model_206ax.h> #include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -486,6 +487,8 @@ static const struct pci_driver mc_driver_1 __pci_driver = { static void cpu_bus_init(device_t dev) { initialize_cpus(dev->link_list); + /* Enable ROM caching if option was selected. */ + x86_mtrr_enable_rom_caching(); } static void cpu_bus_noop(device_t dev) |