diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-10-27 17:00:21 -0600 |
|---|---|---|
| committer | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-11-01 21:58:44 +0000 |
| commit | cbb78cd75251a6677636a08c43da7711adeca204 (patch) | |
| tree | 1dad059bbbec291b59c30295620081f40bd768c4 /src | |
| parent | 14ef26b07b2f2d0150005e85de45af672e2b492d (diff) | |
| download | coreboot-cbb78cd75251a6677636a08c43da7711adeca204.tar.xz | |
amd/stoneyridge: Add definitions for various NB registers
Add #define values for the first MMIO base/limit, the first I/O
base/limit, and VGA enable registers.
Change-Id: I2c209224d356cf3f83a0ddb37974831611a89760
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/northbridge.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index 45c67c22fd..911387836a 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -26,9 +26,20 @@ # define CPU_CNT_MASK 0x1f /* CpuCnt + 1 = no. CPUs */ /* D18F1 - Address Map Registers */ +#define D18F1_MMIO_BASE0_LO 0x80 +# define MMIO_WE (1 << 1) +# define MMIO_RE (1 << 0) +#define D18F1_MMIO_LIMIT0_LO 0x84 +# define MMIO_NP (1 << 7) +#define D18F1_IO_BASE0 0xc0 +# define IO_WE (1 << 1) +# define IO_RE (1 << 0) +#define D18F1_IO_LIMIT0 0xc4 #define D18F1_DRAM_HOLE 0xf0 # define DRAM_HOIST_VALID (1 << 1) # define DRAM_HOLE_VALID (1 << 0) +#define D18F1_VGAEN 0xf4 +# define VGA_ADDR_ENABLE (1 << 0) enum { /* SMM handler area. */ |