diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2013-05-21 09:28:28 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-11-25 23:32:14 +0100 |
| commit | cd7bb2faab769a16bacac8bcbfa20fec970dce16 (patch) | |
| tree | 4879c3251297674d4ede417c5cab97069cffa8a2 /src | |
| parent | 8992e53c23cb088efbdafbf3e2ba77e7d8778d71 (diff) | |
| download | coreboot-cd7bb2faab769a16bacac8bcbfa20fec970dce16.tar.xz | |
slippy: Enable EC SMI
Enable GPIO SMI for GPIO34 and set it as inverted so it
is only generated when it is raised by the EC.
1) ec console command: lidopen
2) wait until booted to developer screen
3) ec console command: lidclose
4) ensure system turns off
Change-Id: I7d50f171f3f4539c7c264103d1ffc7c5d0f1c7ba
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56052
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4177
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/slippy/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/lp_gpio.h | 2 |
2 files changed, 3 insertions, 2 deletions
diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb index 79fea8b89b..b9bc47fb17 100644 --- a/src/mainboard/google/slippy/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -57,7 +57,8 @@ chip northbridge/intel/haswell register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x00fc0901" - register "alt_gp_smi_en" = "0x0000" + # EC_SMI is GPIO34 + register "alt_gp_smi_en" = "0x0004" register "gpe0_en_1" = "0x00000000" # EC_SCI is GPIO36 register "gpe0_en_2" = "0x00000010" diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h index 48a23cb084..d9927dc975 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.h +++ b/src/southbridge/intel/lynxpoint/lp_gpio.h @@ -110,7 +110,7 @@ .route = GPIO_ROUTE_SCI } #define LP_GPIO_ACPI_SMI \ - { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \ .owner = GPIO_OWNER_ACPI, \ .route = GPIO_ROUTE_SMI } |