AGESA: Move API interface under drivers/

New AGESA support files will be used for binaryPI
platforms as well. Furthermore, some of those should
move from split nb/ sb/ directories to soc/, so move
support files for the API under drivers/.

Change-Id: I549788091de91f61de8b9adc223d52ffb5732235
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

26 files changed, 71 insertions, 75 deletions

diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
index 6a7ec8750f..4605dd3ba9 100644
--- a/src/cpu/amd/agesa/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -25,6 +25,7 @@ config CPU_AMD_AGESA
 	select ARCH_VERSTAGE_X86_32
 	select ARCH_ROMSTAGE_X86_32
 	select ARCH_RAMSTAGE_X86_32
+	select DRIVERS_AMD_PI
 	select TSC_SYNC_LFENCE
 	select UDELAY_LAPIC
 	select LAPIC_MONOTONIC_TIMER
diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc
index f4ec2ce0b0..470e62f25d 100644
--- a/src/cpu/amd/agesa/Makefile.inc
+++ b/src/cpu/amd/agesa/Makefile.inc
@@ -18,20 +18,10 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += family15
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb
 
-ramstage-y += s3_mtrr.c
-
 ifeq ($(CONFIG_AGESA_LEGACY), y)
 cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram_legacy.inc
-else
-cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram.S
-romstage-y += romstage.c mtrr_fixme.c
 endif
 
-romstage-$(CONFIG_AGESA_LEGACY_WRAPPER) += heapmanager.c
-
-postcar-y += cache_as_ram.S
-
-ramstage-y += heapmanager.c
 ramstage-$(CONFIG_AGESA_LEGACY_WRAPPER) += amd_late_init.c
 
 ifeq ($(CONFIG_HAVE_ACPI_RESUME), y)
diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c
index 3103dd5d3b..2cfb9090c8 100644
--- a/src/cpu/amd/agesa/family14/model_14_init.c
+++ b/src/cpu/amd/agesa/family14/model_14_init.c
@@ -28,7 +28,7 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/amdfam14.h>
 #include <arch/acpi.h>
-#include <cpu/amd/agesa/s3_resume.h>
+#include <northbridge/amd/agesa/agesa_helper.h>
 
 #define MCI_STATUS 0x401
 
diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c
index fa4a691b9b..f569de7f80 100644
--- a/src/cpu/amd/agesa/family15tn/model_15_init.c
+++ b/src/cpu/amd/agesa/family15tn/model_15_init.c
@@ -29,7 +29,7 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/amdfam15.h>
 #include <arch/acpi.h>
-#include <cpu/amd/agesa/s3_resume.h>
+#include <northbridge/amd/agesa/agesa_helper.h>
 
 static void model_15_init(device_t dev)
 {
diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c
index a8d076c2ad..acfa3f2436 100644
--- a/src/cpu/amd/agesa/family16kb/model_16_init.c
+++ b/src/cpu/amd/agesa/family16kb/model_16_init.c
@@ -28,7 +28,7 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/amdfam16.h>
 #include <arch/acpi.h>
-#include <cpu/amd/agesa/s3_resume.h>
+#include <northbridge/amd/agesa/agesa_helper.h>
 
 static void model_16_init(device_t dev)
 {
diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h
deleted file mode 100644
index 4a7ccb591d..0000000000
--- a/src/cpu/amd/agesa/s3_resume.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef S3_RESUME_H
-#define S3_RESUME_H
-
-void restore_mtrr(void);
-
-void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size);
-const void *OemS3Saved_MTRR_Storage(void);
-
-#endif
diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig
index d71b8321a0..8dc7f5abf9 100644
--- a/src/cpu/amd/pi/Kconfig
+++ b/src/cpu/amd/pi/Kconfig
@@ -23,6 +23,7 @@ config CPU_AMD_PI
 	select ARCH_VERSTAGE_X86_32
 	select ARCH_ROMSTAGE_X86_32
 	select ARCH_RAMSTAGE_X86_32
+	select DRIVERS_AMD_PI
 	select TSC_SYNC_LFENCE
 	select UDELAY_LAPIC
 	select LAPIC_MONOTONIC_TIMER
diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc
index ba9ac265e9..c6d4532dc4 100644
--- a/src/cpu/amd/pi/Makefile.inc
+++ b/src/cpu/amd/pi/Makefile.inc
@@ -17,16 +17,7 @@ subdirs-$(CONFIG_CPU_AMD_PI_00630F01) += 00630F01
 subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01
 subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01
 
-cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram.S
-postcar-y += ../agesa/cache_as_ram.S
-
 ifeq ($(CONFIG_BINARYPI_LEGACY_WRAPPER), y)
 romstage-y += romstage.c
 ramstage-y += amd_late_init.c
-romstage-y += ../agesa/heapmanager.c
-else
-romstage-y += ../agesa/romstage.c
-romstage-y += ../agesa/mtrr_fixme.c
 endif
-
-ramstage-y += ../agesa/heapmanager.c
diff --git a/src/drivers/amd/agesa/Kconfig b/src/drivers/amd/agesa/Kconfig
new file mode 100644
index 0000000000..f667b95fc5
--- /dev/null
+++ b/src/drivers/amd/agesa/Kconfig
@@ -0,0 +1,15 @@
+#
+# This file is part of the coreboot project.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+
+config DRIVERS_AMD_PI
+	def_bool n
diff --git a/src/drivers/amd/agesa/Makefile.inc b/src/drivers/amd/agesa/Makefile.inc
new file mode 100644
index 0000000000..4d3dbf5cb9
--- /dev/null
+++ b/src/drivers/amd/agesa/Makefile.inc
@@ -0,0 +1,44 @@
+#
+# This file is part of the coreboot project.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+
+ifeq ($(CONFIG_DRIVERS_AMD_PI),y)
+
+ifneq ($(CONFIG_AGESA_LEGACY_WRAPPER)$(CONFIG_BINARYPI_LEGACY_WRAPPER),y)
+
+romstage-y += romstage.c
+romstage-y += mtrr_fixme.c
+romstage-y += state_machine.c
+
+ramstage-y += state_machine.c
+
+cpu_incs-y += $(src)/drivers/amd/agesa/cache_as_ram.S
+postcar-y += cache_as_ram.S
+
+else
+
+romstage-y += heapmanager.c
+
+endif
+
+romstage-y += def_callouts.c
+romstage-y += eventlog.c
+
+ramstage-y += def_callouts.c
+ramstage-y += eventlog.c
+ramstage-y += heapmanager.c
+ramstage-y += acpi_tables.c
+
+romstage-$(CONFIG_CPU_AMD_AGESA) += oem_s3.c
+ramstage-$(CONFIG_CPU_AMD_AGESA) += oem_s3.c s3_mtrr.c
+
+endif
diff --git a/src/northbridge/amd/agesa/acpi_tables.c b/src/drivers/amd/agesa/acpi_tables.c
index 5335c02f5b..5335c02f5b 100644
--- a/src/northbridge/amd/agesa/acpi_tables.c
+++ b/src/drivers/amd/agesa/acpi_tables.c
diff --git a/src/cpu/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S
index 50242f7a54..50242f7a54 100644
--- a/src/cpu/amd/agesa/cache_as_ram.S
+++ b/src/drivers/amd/agesa/cache_as_ram.S
diff --git a/src/northbridge/amd/agesa/def_callouts.c b/src/drivers/amd/agesa/def_callouts.c
index e0999266f4..21530a1e00 100644
--- a/src/northbridge/amd/agesa/def_callouts.c
+++ b/src/drivers/amd/agesa/def_callouts.c
@@ -22,8 +22,8 @@
 #include "amdlib.h"
 #include "Ids.h"
 #include <northbridge/amd/agesa/state_machine.h>
-#include "BiosCallOuts.h"
-#include "dimmSpd.h"
+#include <northbridge/amd/agesa/BiosCallOuts.h>
+#include <northbridge/amd/agesa/dimmSpd.h>
 
 #if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI)
 #if IS_ENABLED(CONFIG_ARCH_ROMSTAGE_X86_64) || \
diff --git a/src/northbridge/amd/agesa/eventlog.c b/src/drivers/amd/agesa/eventlog.c
index 33e5590530..33e5590530 100644
--- a/src/northbridge/amd/agesa/eventlog.c
+++ b/src/drivers/amd/agesa/eventlog.c
diff --git a/src/cpu/amd/agesa/heapmanager.c b/src/drivers/amd/agesa/heapmanager.c
index 04775cd36e..04775cd36e 100644
--- a/src/cpu/amd/agesa/heapmanager.c
+++ b/src/drivers/amd/agesa/heapmanager.c
diff --git a/src/cpu/amd/agesa/mtrr_fixme.c b/src/drivers/amd/agesa/mtrr_fixme.c
index 1fbb55318d..1fbb55318d 100644
--- a/src/cpu/amd/agesa/mtrr_fixme.c
+++ b/src/drivers/amd/agesa/mtrr_fixme.c
diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/drivers/amd/agesa/oem_s3.c
index f2cef990db..1ca6e5b2f6 100644
--- a/src/northbridge/amd/agesa/oem_s3.c
+++ b/src/drivers/amd/agesa/oem_s3.c
@@ -18,8 +18,6 @@
 #include <string.h>
 #include <cbmem.h>
 #include <program_loading.h>
-#include <cpu/amd/agesa/s3_resume.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
 #include <northbridge/amd/agesa/state_machine.h>
 #include <AGESA.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
diff --git a/src/cpu/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c
index bd502b6bad..bd502b6bad 100644
--- a/src/cpu/amd/agesa/romstage.c
+++ b/src/drivers/amd/agesa/romstage.c
diff --git a/src/cpu/amd/agesa/s3_mtrr.c b/src/drivers/amd/agesa/s3_mtrr.c
index 519198913f..c039abefb6 100644
--- a/src/cpu/amd/agesa/s3_mtrr.c
+++ b/src/drivers/amd/agesa/s3_mtrr.c
@@ -19,7 +19,7 @@
 #include <cpu/amd/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <string.h>
-#include "s3_resume.h"
+#include <northbridge/amd/agesa/agesa_helper.h>
 
 static void write_mtrr(u8 **p_nvram_pos, unsigned idx)
 {
diff --git a/src/northbridge/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c
index 015d445ab9..fdd2e6eeac 100644
--- a/src/northbridge/amd/agesa/state_machine.c
+++ b/src/drivers/amd/agesa/state_machine.c
@@ -26,7 +26,6 @@
 #include <northbridge/amd/agesa/agesa_helper.h>
 #include <northbridge/amd/agesa/BiosCallOuts.h>
 #include "amdlib.h"
-#include <cpu/amd/agesa/s3_resume.h>
 
 #include "AMD.h"
 
diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc
index 2c39b5124f..7de920e616 100644
--- a/src/northbridge/amd/agesa/Makefile.inc
+++ b/src/northbridge/amd/agesa/Makefile.inc
@@ -21,18 +21,9 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15) += family15
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN) += family15tn
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB) += family16kb
 
-romstage-y += def_callouts.c eventlog.c
-ramstage-y += def_callouts.c eventlog.c acpi_tables.c
-
 ifeq ($(CONFIG_AGESA_LEGACY_WRAPPER), y)
 romstage-y += agesawrapper.c
 ramstage-y += agesawrapper.c
-else
-romstage-y += state_machine.c
-ramstage-y += state_machine.c
 endif
 
-romstage-y += oem_s3.c
-ramstage-y += oem_s3.c
-
 endif
diff --git a/src/northbridge/amd/agesa/agesa_helper.h b/src/northbridge/amd/agesa/agesa_helper.h
index 044393d4b9..17819e9567 100644
--- a/src/northbridge/amd/agesa/agesa_helper.h
+++ b/src/northbridge/amd/agesa/agesa_helper.h
@@ -57,4 +57,8 @@ void EmptyHeap(void);
 void fixup_cbmem_to_UC(int s3resume);
 void recover_postcar_frame(struct postcar_frame *pcf, int s3resume);
 
+void restore_mtrr(void);
+void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size);
+const void *OemS3Saved_MTRR_Storage(void);
+
 #endif /* _AGESA_HELPER_H_ */
diff --git a/src/northbridge/amd/agesa/agesawrapper.c b/src/northbridge/amd/agesa/agesawrapper.c
index 87a39a9f2b..768f10042f 100644
--- a/src/northbridge/amd/agesa/agesawrapper.c
+++ b/src/northbridge/amd/agesa/agesawrapper.c
@@ -22,7 +22,6 @@
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <northbridge/amd/agesa/BiosCallOuts.h>
 #include "amdlib.h"
-#include <cpu/amd/agesa/s3_resume.h>
 
 #include "heapManager.h"
 
diff --git a/src/northbridge/amd/agesa/family12/state_machine.c b/src/northbridge/amd/agesa/family12/state_machine.c
index ed216c74fb..52b065e9e3 100644
--- a/src/northbridge/amd/agesa/family12/state_machine.c
+++ b/src/northbridge/amd/agesa/family12/state_machine.c
@@ -20,8 +20,6 @@
 #include <northbridge/amd/agesa/state_machine.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 
-#include <cpu/amd/agesa/s3_resume.h>
-
 #include <sb_cimx.h>
 
 void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
diff --git a/src/northbridge/amd/pi/Makefile.inc b/src/northbridge/amd/pi/Makefile.inc
index 93c87ecc68..c2c8d8818d 100644
--- a/src/northbridge/amd/pi/Makefile.inc
+++ b/src/northbridge/amd/pi/Makefile.inc
@@ -22,18 +22,8 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00660F01) += 00660F01
 ifeq ($(CONFIG_BINARYPI_LEGACY_WRAPPER), y)
 romstage-y += agesawrapper.c
 ramstage-y += agesawrapper.c
-else
-romstage-y += ../agesa/state_machine.c
-ramstage-y += ../agesa/state_machine.c
-
-romstage-y += ../agesa/eventlog.c
-ramstage-y += ../agesa/eventlog.c
-
 endif
 
-romstage-y += ../agesa/def_callouts.c ../agesa/eventlog.c
-ramstage-y += ../agesa/def_callouts.c ../agesa/eventlog.c ../agesa/acpi_tables.c
-
 romstage-y += ramtop.c
 postcar-y += ramtop.c
 ramstage-y += ramtop.c
diff --git a/src/southbridge/amd/agesa/hudson/resume.c b/src/southbridge/amd/agesa/hudson/resume.c
index e680fadf31..2528294a7d 100644
--- a/src/southbridge/amd/agesa/hudson/resume.c
+++ b/src/southbridge/amd/agesa/hudson/resume.c
@@ -15,7 +15,6 @@
 
 #include <Proc/Fch/FchPlatform.h>
 #include <Proc/Fch/Fch.h>
-#include <cpu/amd/agesa/s3_resume.h>
 #include <device/device.h>
 #include "hudson.h"
 #include "AGESA.h"