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| author | Frans Hendriks <fhendriks@eltan.com> | 2018-11-26 11:01:56 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-28 11:47:01 +0000 |
| commit | d97eb646e75e33c5a4068c21fb20b75ef2acb820 (patch) | |
| tree | 5cae30f50aaa3f2cba76505242dc75dfd52c18bf /src | |
| parent | f01a15952adb903fed169dbcef1e4a33cc88ba3f (diff) | |
| download | coreboot-d97eb646e75e33c5a4068c21fb20b75ef2acb820.tar.xz | |
soc/intel/braswell/northcluster.c: Reserve local APIC resources
The resources of the local APIC are not reserved.
Use mmio_resource() to add local APIC resources.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: Ieb9de45098d507d59f1974eddb7a94cb18ef7903
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/braswell/northcluster.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index 40d658c4d4..dcd98b54b1 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -21,6 +21,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <fsp/memmap.h> +#include <cpu/x86/lapic.h> #include <fsp/util.h> #include <soc/iomap.h> #include <soc/iosf.h> @@ -148,6 +149,13 @@ static void nc_read_resources(struct device *dev) reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); + /* + * Reserve local APIC + */ + base_k = RES_IN_KIB(LAPIC_DEFAULT_BASE); + size_k = RES_IN_KIB(0x00100000); + mmio_resource(dev, index++, base_k, size_k); + chromeos_reserve_ram_oops(dev, index++); } |