diff options
author | Aaron Durbin <adurbin@chromium.org> | 2014-08-27 17:25:18 -0500 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-27 08:04:12 +0100 |
commit | da185c17028c8dbef0d57ba3624a50ef1ebd00a0 (patch) | |
tree | 4bb3d2c24c0524a5fd903af9a3df9707cb575cf6 /src | |
parent | 97b78cba5afd1636a306cc6533f8abd0a886483a (diff) | |
download | coreboot-da185c17028c8dbef0d57ba3624a50ef1ebd00a0.tar.xz |
arm64: provide API for coordinating secondary CPU bringup
Provides a minimal API for coordinating with the SoC for
bringing up the secondary CPUs. There's no eventloop or
dispatcher currently nor does it do anything proper when
one of the secondary CPUs are brought up. Those decisions
are deferred to the SoC.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and brought up 2nd cpu using this API.
Change-Id: I8ac0418282e2e5b4ab3abfd21c88f51d704e10f9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5303ae3d6bfc9f8f908fcb890e184eb9b57f1376
Original-Change-Id: I3b7334b7d2df2df093cdc0cbb997e8230d3b2685
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214775
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9019
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r-- | src/arch/arm64/c_entry.c | 32 | ||||
-rw-r--r-- | src/arch/arm64/include/armv8/arch/cpu.h | 13 |
2 files changed, 43 insertions, 2 deletions
diff --git a/src/arch/arm64/c_entry.c b/src/arch/arm64/c_entry.c index 3e9d44e4af..869518785b 100644 --- a/src/arch/arm64/c_entry.c +++ b/src/arch/arm64/c_entry.c @@ -17,9 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/stages.h> +#include <arch/cache.h> #include <arch/cpu.h> - +#include <arch/exception.h> +#include <arch/mmu.h> +#include <arch/stages.h> /* * This variable holds entry point for CPUs starting up. Before the other @@ -33,6 +35,11 @@ void __attribute__((weak)) arm64_soc_init(void) /* Default weak implementation does nothing. */ } +void __attribute__((weak)) soc_secondary_cpu_init(void) +{ + /* Default weak implementation does nothing. */ +} + static void seed_stack(void) { char *stack_begin; @@ -57,3 +64,24 @@ void arm64_init(void) arm64_soc_init(); main(); } + +static void secondary_cpu_start(void) +{ + mmu_enable(); + exception_hwinit(); + soc_secondary_cpu_init(); + /* + * TODO(adurbin): need a proper place to park the CPUs. Currently + * assuming SoC code does the appropriate thing. + */ + while (1); +} + +extern void arm64_cpu_startup(void); +void *prepare_secondary_cpu_startup(void) +{ + c_entry = &secondary_cpu_start; + dcache_clean_invalidate_by_mva(c_entry, sizeof(c_entry)); + + return &arm64_cpu_startup; +} diff --git a/src/arch/arm64/include/armv8/arch/cpu.h b/src/arch/arm64/include/armv8/arch/cpu.h index e80e739133..5ce9ba3ab5 100644 --- a/src/arch/arm64/include/armv8/arch/cpu.h +++ b/src/arch/arm64/include/armv8/arch/cpu.h @@ -58,4 +58,17 @@ void *cpu_get_stack(unsigned int cpu); /* Return the top of the exception stack for the specified cpu. */ void *cpu_get_exception_stack(unsigned int cpu); +/* + * Do the necessary work to prepare for secondary CPUs coming up. The + * SoC will call this function before bringing up the other CPUs. The + * entry point for the seoncdary CPUs is returned. + */ +void *prepare_secondary_cpu_startup(void); + +/* + * Function provided by the SoC code that is called for each secondary + * CPU startup. + */ +void soc_secondary_cpu_init(void); + #endif /* __ARCH_CPU_H__ */ |