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author | Ward Vandewege <ward@gnu.org> | 2008-08-08 00:08:01 +0000 |
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committer | Ward Vandewege <ward@gnu.org> | 2008-08-08 00:08:01 +0000 |
commit | dc93affe72b4e3162fde653da5c0ea0c84bd5e39 (patch) | |
tree | 781b1b8727a9fdf0c2fc4a23a8085aff8eb25f2b /src | |
parent | a2c951edf7de94d64acd31e20b3fea7d3e869069 (diff) | |
download | coreboot-dc93affe72b4e3162fde653da5c0ea0c84bd5e39.tar.xz |
Enable both IDE ports for our qemu target.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3481 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r-- | src/mainboard/emulation/qemu-x86/Config.lb | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/mainboard/emulation/qemu-x86/Config.lb b/src/mainboard/emulation/qemu-x86/Config.lb index f159772c6b..b6f3e90fe8 100644 --- a/src/mainboard/emulation/qemu-x86/Config.lb +++ b/src/mainboard/emulation/qemu-x86/Config.lb @@ -107,7 +107,14 @@ config chip.h chip cpu/emulation/qemu-x86 device pci_domain 0 on device pci 0.0 on end - device pci 1.0 on end + + chip southbridge/intel/i82371eb # southbridge + device pci 01.0 on end + device pci 01.1 on end + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + # register "com1" = "{1}" # register "com1" = "{1, 0, 0x3f8, 4}" end |