diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2014-10-30 15:23:52 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-14 12:12:42 +0200 |
| commit | dfdc2bac858c1b7a026b4619e07b8f6072171928 (patch) | |
| tree | fe460d026cfac29a77685adbb71efd91cb52af50 /src | |
| parent | b22765e0c76e909fe8dc74b9f8f86fc65f278c5e (diff) | |
| download | coreboot-dfdc2bac858c1b7a026b4619e07b8f6072171928.tar.xz | |
samus: Declare TPM in devicetree.cb and include ACPI device
This adds the TPM device to the devicetree and configures an
active high edge triggered interrupt at IRQ10 and adds the ACPI
Device for the TPM into the DSDT.
It also cleans up the EC PNP ID to use the EISAID for an EC since
there are now two PNP devices declared, and removes the unused
ENABLE_TPM define at the top of the DSDT.
BUG=chrome-os-partner:33385
BRANCH=samus
TEST=build and boot on samus, ensure TPM is functional at IRQ10
CQ-DEPEND=CL:226661
Change-Id: I4b9b016014d136fbf9a37003003632821ae93a53
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 0420e27b05d0f1568efa9beb849e0e8ff5995c86
Original-Change-Id: I2660cb30ac535da0b255603a619b9c09681ca947
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/226663
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9471
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/samus/acpi/mainboard.asl | 8 | ||||
| -rw-r--r-- | src/mainboard/google/samus/devicetree.cb | 13 | ||||
| -rw-r--r-- | src/mainboard/google/samus/dsdt.asl | 2 |
3 files changed, 16 insertions, 7 deletions
diff --git a/src/mainboard/google/samus/acpi/mainboard.asl b/src/mainboard/google/samus/acpi/mainboard.asl index 918e56580b..2140898809 100644 --- a/src/mainboard/google/samus/acpi/mainboard.asl +++ b/src/mainboard/google/samus/acpi/mainboard.asl @@ -58,6 +58,14 @@ Scope (\_SB) } /* + * LPC Trusted Platform Module + */ +Scope (\_SB.PCI0.LPCB) +{ + #include <drivers/pc80/tpm/acpi/tpm.asl> +} + +/* * WLAN connected to Root Port 3, becomes Root Port 1 after coalesce */ Scope (\_SB.PCI0.RP01) diff --git a/src/mainboard/google/samus/devicetree.cb b/src/mainboard/google/samus/devicetree.cb index b3596a4fa7..d12762d60c 100644 --- a/src/mainboard/google/samus/devicetree.cb +++ b/src/mainboard/google/samus/devicetree.cb @@ -94,13 +94,16 @@ chip soc/intel/broadwell device pci 1d.0 off end # USB2 EHCI device pci 1e.0 off end # PCI bridge device pci 1f.0 on - chip ec/google/chromeec - # We only have one init function that - # we need to call to initialize the - # keyboard part of the EC. - device pnp ff.1 on # dummy address + chip drivers/pc80/tpm + # Rising edge interrupt + register "irq_polarity" = "2" + device pnp 0c31.0 on + irq 0x70 = 10 end end + chip ec/google/chromeec + device pnp 0c09.0 on end + end end # LPC bridge device pci 1f.2 on end # SATA Controller device pci 1f.3 off end # SMBus diff --git a/src/mainboard/google/samus/dsdt.asl b/src/mainboard/google/samus/dsdt.asl index cfd20371b0..722e0c9c93 100644 --- a/src/mainboard/google/samus/dsdt.asl +++ b/src/mainboard/google/samus/dsdt.asl @@ -18,8 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ENABLE_TPM - DefinitionBlock( "dsdt.aml", "DSDT", |