diff options
| author | Akshu Agrawal <akshu.agrawal@amd.com> | 2018-03-19 10:30:47 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2018-03-21 03:55:11 +0000 |
| commit | e11a11265b62cc561efcc81dd89a01918953160a (patch) | |
| tree | d73ba5ba3807223902894e5fb186b877ee588efa /src | |
| parent | bf7dea00280b78e5261774958ab04ff45bbbec90 (diff) | |
| download | coreboot-e11a11265b62cc561efcc81dd89a01918953160a.tar.xz | |
mb/google/kahlee: Add register address mapping for FCH MISC
Audio machine driver will enable/disable clock by making it as
a CCF clock in kernel.
BUG=b:74570989
TEST=cherry-picked https://patchwork.kernel.org/patch/10291875/
on 4.14 kernel
aplay -vv <file>
check register to see clock enabled
kill aplay
check register to see clock disabled
Change-Id: Ia553e55ffb358415067000d2d2d2744322d1c4db
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/25263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl index ea58f89a3d..0e7d03f8df 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl @@ -12,7 +12,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - +#include <soc/iomap.h> /* Grunt specific I2S machine driver */ Device (I2S) @@ -20,4 +20,14 @@ Device (I2S) Name (_ADR, 1) Name (_HID, "AMD7219") Name (_CID, "AMD7219") + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () { + // Memory resource is for MISC FCH register set. + // It is needed for enabling the clock. + Memory32Fixed(ReadWrite, MISC_MMIO_BASE, 0x100) + }) + + Return (RBUF) + } } |