diff options
| author | Ed Swierk <eswierk@aristanetworks.com> | 2009-07-10 15:05:35 +0000 |
|---|---|---|
| committer | Ed Swierk <eswierk@arastra.com> | 2009-07-10 15:05:35 +0000 |
| commit | e42e142d9fc0048574664c3c92bdc1bbca35c9be (patch) | |
| tree | 07f78bdcdf580b1804434ec89973be77d1104d57 /src | |
| parent | 7d4fd2c1081a7674c0631cbe96aa23ca51879586 (diff) | |
| download | coreboot-e42e142d9fc0048574664c3c92bdc1bbca35c9be.tar.xz | |
Apparently I'm not the only one who forgets which way the outb and
outl arguments go.
Signed-off-by: Ed Swierk <eswierk@aristanetworks.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4422 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/amd/sc520/raminit.c | 8 | ||||
| -rw-r--r-- | src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c | 2 | ||||
| -rw-r--r-- | src/southbridge/nvidia/ck804/ck804_lpc.c | 2 | ||||
| -rw-r--r-- | src/southbridge/nvidia/mcp55/mcp55_lpc.c | 2 | ||||
| -rw-r--r-- | src/southbridge/sis/sis966/sis966_lpc.c | 2 |
5 files changed, 8 insertions, 8 deletions
diff --git a/src/cpu/amd/sc520/raminit.c b/src/cpu/amd/sc520/raminit.c index 1845c629c2..d20280761d 100644 --- a/src/cpu/amd/sc520/raminit.c +++ b/src/cpu/amd/sc520/raminit.c @@ -183,16 +183,16 @@ void setupsc520(void) /* Stepan says: This needs to go to the msm586seg code */ /* "enumerate" the PCI. Mainly set the interrupt bits on the PCnetFast. */ - outl(0xcf8, 0x08000683c); - outl(0xcfc, 0xc); /* set the interrupt line */ + outl(0x08000683c, 0xcf8); + outl(0xc, 0xcfc); /* set the interrupt line */ /* Set the SC520 PCI host bridge to target mode to * allow external bus mastering events */ /* index the status command register on device 0*/ - outl(0x0cf8,0x080000004); - outl(0xcfc, 0x2); /*set the memory access enable bit*/ + outl(0x080000004, 0x0cf8); + outl(0x2, 0xcfc); /*set the memory access enable bit*/ OUTC(0x0fffef072, 1); /* enable req bits in SYSARBMENB */ } diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c b/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c index 34381eaa29..69e077ebb0 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c @@ -38,7 +38,7 @@ static void sb_init(device_t dev) byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW } if( byte != byte_old) { - outb(0x70, byte); + outb(byte, 0x70); } diff --git a/src/southbridge/nvidia/ck804/ck804_lpc.c b/src/southbridge/nvidia/ck804/ck804_lpc.c index 5bdcecd78f..546c27a8fd 100644 --- a/src/southbridge/nvidia/ck804/ck804_lpc.c +++ b/src/southbridge/nvidia/ck804/ck804_lpc.c @@ -245,7 +245,7 @@ static void lpc_init(device_t dev) byte |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW. */ } if (byte != byte_old) - outb(0x70, byte); + outb(byte, 0x70); /* Initialize the real time clock (RTC). */ rtc_init(0); diff --git a/src/southbridge/nvidia/mcp55/mcp55_lpc.c b/src/southbridge/nvidia/mcp55/mcp55_lpc.c index 480394ea09..a9e6c36991 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_lpc.c +++ b/src/southbridge/nvidia/mcp55/mcp55_lpc.c @@ -230,7 +230,7 @@ static void lpc_init(device_t dev) byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW } if( byte != byte_old) { - outb(0x70, byte); + outb(byte, 0x70); } /* Initialize the real time clock */ diff --git a/src/southbridge/sis/sis966/sis966_lpc.c b/src/southbridge/sis/sis966/sis966_lpc.c index c6762a9cdb..dd369b694b 100644 --- a/src/southbridge/sis/sis966/sis966_lpc.c +++ b/src/southbridge/sis/sis966/sis966_lpc.c @@ -220,7 +220,7 @@ static void lpc_init(device_t dev) byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW } if( byte != byte_old) { - outb(0x70, byte); + outb(byte, 0x70); } /* Initialize the real time clock */ |