Fix a LOT of implicit function declarations before they become errors.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3822 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

17 files changed, 24 insertions, 2 deletions

diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c
index 607de0bccf..d7b77efb72 100644
--- a/src/cpu/intel/model_f2x/model_f2x_init.c
+++ b/src/cpu/intel/model_f2x/model_f2x_init.c
@@ -8,6 +8,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/lapic.h>
 #include <cpu/intel/microcode.h>
+#include <cpu/intel/hyperthreading.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/mtrr.h>
 
diff --git a/src/include/pc80/keyboard.h b/src/include/pc80/keyboard.h
index 775dbee6e4..33ac913de8 100644
--- a/src/include/pc80/keyboard.h
+++ b/src/include/pc80/keyboard.h
@@ -6,5 +6,6 @@ struct pc_keyboard {
 };
 
 void init_pc_keyboard(unsigned port0, unsigned port1, struct pc_keyboard *kbd);
+void set_kbc_ps2_mode(void);
 
 #endif /* PC80_KEYBOARD_H */
diff --git a/src/mainboard/amd/pistachio/fadt.c b/src/mainboard/amd/pistachio/fadt.c
index cf0a370be1..d03ea5c796 100644
--- a/src/mainboard/amd/pistachio/fadt.c
+++ b/src/mainboard/amd/pistachio/fadt.c
@@ -26,6 +26,7 @@
 #include <arch/acpi.h>
 #include <arch/io.h>
 
+extern void pm_iowrite(u8 reg, u8 value);
 /*extern*/ u16 pm_base = 0x800;
 /* pm_base should be set in sb acpi */
 /* pm_base should be got from bar2 of rs690. Here I compact ACPI
diff --git a/src/mainboard/amd/pistachio/mainboard.c b/src/mainboard/amd/pistachio/mainboard.c
index 96ea307919..82ee4c0b97 100644
--- a/src/mainboard/amd/pistachio/mainboard.c
+++ b/src/mainboard/amd/pistachio/mainboard.c
@@ -37,6 +37,9 @@ extern void pm2_iowrite(u8 reg, u8 value);
 extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
 extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
 			       u8 val);
+extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type, 
+				uint64_t start, uint64_t size);
+
 #define ADT7475_read_byte(address) \
 	 do_smbus_read_byte(SMBUS_IO_BASE, ADT7475_ADDRESS, address)
 #define ADT7475_write_byte(address, val) \
diff --git a/src/mainboard/dell/s1850/reset.c b/src/mainboard/dell/s1850/reset.c
index 06d8886d8d..cf9e3d8d69 100644
--- a/src/mainboard/dell/s1850/reset.c
+++ b/src/mainboard/dell/s1850/reset.c
@@ -1,4 +1,5 @@
 #include <arch/io.h>
+#include <device/pci.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #ifndef __ROMCC__
diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c
index 2c7c9813c2..afe18a1255 100644
--- a/src/northbridge/amd/amdk8/northbridge.c
+++ b/src/northbridge/amd/amdk8/northbridge.c
@@ -16,6 +16,7 @@
 #include <string.h>
 #include <bitops.h>
 #include <cpu/cpu.h>
+#include <cpu/amd/model_fxx_rev.h>
 
 #include <cpu/x86/lapic.h>
 
diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c
index f2e020bd2e..5a01979c0a 100644
--- a/src/northbridge/amd/gx1/northbridge.c
+++ b/src/northbridge/amd/gx1/northbridge.c
@@ -11,6 +11,7 @@
 #include "northbridge.h"
 #include <cpu/amd/gx1def.h>
 #include <cpu/x86/cache.h>
+#include <cpu/cpu.h>
 
 #define NORTHBRIDGE_FILE "northbridge.c"
 /*
diff --git a/src/northbridge/amd/gx2/chipsetinit.c b/src/northbridge/amd/gx2/chipsetinit.c
index e75135d719..53a90535a5 100644
--- a/src/northbridge/amd/gx2/chipsetinit.c
+++ b/src/northbridge/amd/gx2/chipsetinit.c
@@ -14,7 +14,7 @@
 #include <cpu/x86/cache.h>
 #include "../../../southbridge/amd/cs5536/cs5536.h"
 
-
+extern int sizeram(void);
 /* the structs in this file only set msr.lo. But ... that may not always be true */
 
 struct msrinit {
diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c
index c035931ebe..7702d3b5a7 100644
--- a/src/northbridge/amd/gx2/northbridge.c
+++ b/src/northbridge/amd/gx2/northbridge.c
@@ -13,6 +13,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/cache.h>
 #include <cpu/amd/vr.h>
+#include <cpu/cpu.h>
 #include "../../../southbridge/amd/cs5536/cs5536.h"
 #define VIDEO_MB 8
 
diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c
index ead274b729..588023cbbc 100644
--- a/src/northbridge/amd/lx/northbridge.c
+++ b/src/northbridge/amd/lx/northbridge.c
@@ -32,6 +32,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/cache.h>
 #include <cpu/amd/vr.h>
+#include <cpu/cpu.h>
 #include "chip.h"
 #include "northbridge.h"
 #include "../../../southbridge/amd/cs5536/cs5536.h"
diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c
index 9f88d3c120..306e73e66d 100644
--- a/src/northbridge/intel/i440bx/northbridge.c
+++ b/src/northbridge/intel/i440bx/northbridge.c
@@ -7,6 +7,8 @@
 #include <stdlib.h>
 #include <string.h>
 #include <bitops.h>
+#include <cpu/cpu.h>
+#include <pc80/keyboard.h>
 #include "chip.h"
 #include "northbridge.h"
 #include "i440bx.h"
diff --git a/src/northbridge/intel/i855pm/northbridge.c b/src/northbridge/intel/i855pm/northbridge.c
index a0259e72f3..85adf4f417 100644
--- a/src/northbridge/intel/i855pm/northbridge.c
+++ b/src/northbridge/intel/i855pm/northbridge.c
@@ -3,6 +3,7 @@
 #include <stdint.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <device/pci_ids.h>
 #include <stdlib.h>
 #include <string.h>
 #include <bitops.h>
@@ -13,7 +14,6 @@
 static void pci_domain_read_resources(device_t dev)
 {
         struct resource *resource;
-        unsigned reg;
 
         /* Initialize the system wide io space constraints */
         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
diff --git a/src/southbridge/via/k8t890/k8t890.h b/src/southbridge/via/k8t890/k8t890.h
index 63f8d20926..9159b53d5c 100644
--- a/src/southbridge/via/k8t890/k8t890.h
+++ b/src/southbridge/via/k8t890/k8t890.h
@@ -35,4 +35,8 @@
 /* the FB size in MB (min is 8MB max is 512MB) */
 #define K8M890_FBSIZEMB		64
 
+#include <device/device.h>
+extern void writeback(struct device *dev, u16 where, u8 what);
+extern void dump_south(device_t dev);
+
 #endif
diff --git a/src/southbridge/via/k8t890/k8t890_bridge.c b/src/southbridge/via/k8t890/k8t890_bridge.c
index 44347127f6..1948246eea 100644
--- a/src/southbridge/via/k8t890/k8t890_bridge.c
+++ b/src/southbridge/via/k8t890/k8t890_bridge.c
@@ -21,6 +21,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <console/console.h>
+#include "k8t890.h"
 
 static void bridge_enable(struct device *dev)
 {
diff --git a/src/southbridge/via/k8t890/k8t890_host_ctrl.c b/src/southbridge/via/k8t890/k8t890_host_ctrl.c
index faa498e8b0..71f863bdc8 100644
--- a/src/southbridge/via/k8t890/k8t890_host_ctrl.c
+++ b/src/southbridge/via/k8t890/k8t890_host_ctrl.c
@@ -22,6 +22,7 @@
 #include <device/pci_ops.h>
 #include <device/pci_ids.h>
 #include <console/console.h>
+#include "k8t890.h"
 
 /* this may be later merged */
 
diff --git a/src/southbridge/via/k8t890/k8t890_pcie.c b/src/southbridge/via/k8t890/k8t890_pcie.c
index 6a7acbbfed..5d74152fd2 100644
--- a/src/southbridge/via/k8t890/k8t890_pcie.c
+++ b/src/southbridge/via/k8t890/k8t890_pcie.c
@@ -22,6 +22,7 @@
 #include <device/pci.h>
 #include <device/pciexp.h>
 #include <device/pci_ids.h>
+#include "k8t890.h"
 
 static void peg_init(struct device *dev)
 {
diff --git a/src/southbridge/via/k8t890/k8t890_traf_ctrl.c b/src/southbridge/via/k8t890/k8t890_traf_ctrl.c
index a61c56d155..a5906cfe31 100644
--- a/src/southbridge/via/k8t890/k8t890_traf_ctrl.c
+++ b/src/southbridge/via/k8t890/k8t890_traf_ctrl.c
@@ -23,6 +23,8 @@
 #include <console/console.h>
 #include "k8t890.h"
 
+extern unsigned long log2(unsigned long x);
+
 static void mmconfig_set_resources(device_t dev)
 {
 	struct resource *resource;