diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2013-12-18 10:55:48 -0800 |
|---|---|---|
| committer | Isaac Christensen <isaac.christensen@se-eng.com> | 2014-09-18 18:31:46 +0200 |
| commit | f7c308edeac2c8886afab13c5e8052cc15d84575 (patch) | |
| tree | 248746eaed37386b9deb546874b7793ef20889c7 /src | |
| parent | d5acaaf8451d727107b53882c9d3bae4482fe0b8 (diff) | |
| download | coreboot-f7c308edeac2c8886afab13c5e8052cc15d84575.tar.xz | |
samus: Enable XHCI mode by default
- Enable xhci_default setting in devicetree
- Enable usb_xhci_on_resume setting for PEI
Change-Id: I2a3965a222ce571a2ad43f568fc2d0ecb94a77bc
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180673
(cherry picked from commit c5ef875f6d148964b8ad62a3fe79916c758dbc57)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6908
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/samus/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/mainboard/google/samus/romstage.c | 1 |
2 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/samus/devicetree.cb b/src/mainboard/google/samus/devicetree.cb index f848edc40b..12a21ecdb0 100644 --- a/src/mainboard/google/samus/devicetree.cb +++ b/src/mainboard/google/samus/devicetree.cb @@ -80,6 +80,9 @@ chip northbridge/intel/haswell # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP register "icc_clock_disable" = "0x013e0000" + # Route all USB ports to XHCI per default + register "xhci_default" = "1" + device pci 13.0 on end # Smart Sound Audio DSP device pci 14.0 on end # USB3 XHCI device pci 15.0 on end # Serial I/O DMA diff --git a/src/mainboard/google/samus/romstage.c b/src/mainboard/google/samus/romstage.c index 7d3c90c0a8..abd93c42e9 100644 --- a/src/mainboard/google/samus/romstage.c +++ b/src/mainboard/google/samus/romstage.c @@ -126,6 +126,7 @@ void mainboard_romstage_entry(unsigned long bist) .dimm_channel0_disabled = 2, .dimm_channel1_disabled = 2, .max_ddr3_freq = 1600, + .usb_xhci_on_resume = 1, .usb2_ports = { /* Length, Enable, OCn#, Location */ { 0x0080, 1, 0, /* P0: HOST PORT */ |