diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-12-05 12:40:08 -0600 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-05-08 07:06:59 +0200 |
| commit | fad3703ce80011ccc0eaef03fb0575f591085d5f (patch) | |
| tree | fde4692d29be56fbdfb275d0a6a066dbb1de26e0 /src | |
| parent | 4334c876346fe6c4ab977ed93a65eed765e7b9bb (diff) | |
| download | coreboot-fad3703ce80011ccc0eaef03fb0575f591085d5f.tar.xz | |
rambi: configure SD card signals
Rambi 1.5 boards use the native SD card controller on baytrail.
Therefore, enable those signals. The CLK, D*, and CMD pins use
2K pulls as these were shown to not exhibit any errors when
doing reads or writes to a DDR50 sd card.
Note that if a servo is connected on needs to enable the
sd_vref_sel rail to pp1800 as this causes issues with card
detect if it is not set to pp1800.
BUG=chrome-os-partner:24312
BRANCH=None
TEST=Built and booted. Tested sd card read and write works in kernel.
Also noted that write protect detection works as well.
Change-Id: I520e2808acbd8494534fcb710411dbc0e12fc874
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178961
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4990
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/rambi/gpio.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/mainboard/google/rambi/gpio.c b/src/mainboard/google/rambi/gpio.c index 76002cfd43..68a5970345 100644 --- a/src/mainboard/google/rambi/gpio.c +++ b/src/mainboard/google/rambi/gpio.c @@ -63,7 +63,7 @@ static const struct soc_gpio_map gpscore_gpio_map[] = { GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */ GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */ GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */ - GPIO_NC, /* S0-SC007 - SD3_WP (NC) */ + GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */ GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ @@ -89,15 +89,15 @@ static const struct soc_gpio_map gpscore_gpio_map[] = { GPIO_NC, /* S0-SC030 - NC */ GPIO_NC, /* S0-SC031 - NC */ GPIO_NC, /* S0-SC032 - NC */ - GPIO_NC, /* S0-SC033 - SD3_CLK (NC) */ - GPIO_NC, /* S0-SC034 - SD3_D0 (NC) */ - GPIO_NC, /* S0-SC035 - SD3_D1 (NC) */ - GPIO_NC, /* S0-SC036 - SD3_D2 (NC) */ - GPIO_NC, /* S0-SC037 - SD3_D3 (NC) */ - GPIO_NC, /* S0-SC038 - SD3_CD# (NC) */ - GPIO_NC, /* S0-SC039 - SD3_CMD (NC) */ - GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN (NC) */ - GPIO_NC, /* S0-SC041 - SDIO3_PWR_EN# (NC)*/ + GPIO_FUNC(1, PULL_DOWN, 2K), /* S0-SC033 - SD3_CLK */ + GPIO_FUNC(1, PULL_UP, 2K), /* S0-SC034 - SD3_D0 */ + GPIO_FUNC(1, PULL_UP, 2K), /* S0-SC035 - SD3_D1 */ + GPIO_FUNC(1, PULL_UP, 2K), /* S0-SC036 - SD3_D2 */ + GPIO_FUNC(1, PULL_UP, 2K), /* S0-SC037 - SD3_D3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ + GPIO_FUNC(1, PULL_UP, 2K), /* S0-SC039 - SD3_CMD */ + GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */ GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ |