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authorStefan Reinauer <stepan@coresystems.de>2009-10-26 16:48:27 +0000
committerStefan Reinauer <stepan@openbios.org>2009-10-26 16:48:27 +0000
commitfbb8a015436d745916bfde6b521b3c36ae534e5e (patch)
treef6df4642d117c65847ca8a4da0a71df35b1b15e3 /src
parent39e722958c80930a0d58a7cb267a0387811be099 (diff)
downloadcoreboot-fbb8a015436d745916bfde6b521b3c36ae534e5e.tar.xz
Use Intel Core code for eagleheights CAR init, not Intel Core 2, as
any of the CPUs might be used. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4858 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/intel/eagleheights/Config.lb3
-rw-r--r--src/mainboard/intel/eagleheights/Makefile.inc1
-rw-r--r--src/mainboard/intel/eagleheights/auto.c3
3 files changed, 5 insertions, 2 deletions
diff --git a/src/mainboard/intel/eagleheights/Config.lb b/src/mainboard/intel/eagleheights/Config.lb
index 8346682908..ea76cad821 100644
--- a/src/mainboard/intel/eagleheights/Config.lb
+++ b/src/mainboard/intel/eagleheights/Config.lb
@@ -109,7 +109,8 @@ ldscript /arch/i386/lib/id.lds
##
## Setup Cache-As-Ram
##
-mainboardinit cpu/intel/model_6fx/cache_as_ram.inc
+## Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
+mainboardinit cpu/intel/model_6ex/cache_as_ram.inc
###
### This is the early phase of coreboot startup
diff --git a/src/mainboard/intel/eagleheights/Makefile.inc b/src/mainboard/intel/eagleheights/Makefile.inc
index 4f4d38c6ec..38ee2af977 100644
--- a/src/mainboard/intel/eagleheights/Makefile.inc
+++ b/src/mainboard/intel/eagleheights/Makefile.inc
@@ -14,6 +14,7 @@ crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
crt0-y += ../../../../src/arch/i386/lib/id.inc
+# Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
crt0-y += ../../../../src/cpu/intel/model_6ex/cache_as_ram.inc
crt0-y += auto.inc
diff --git a/src/mainboard/intel/eagleheights/auto.c b/src/mainboard/intel/eagleheights/auto.c
index f28e1e7bbb..2dce5bb6c3 100644
--- a/src/mainboard/intel/eagleheights/auto.c
+++ b/src/mainboard/intel/eagleheights/auto.c
@@ -238,4 +238,5 @@ void real_main(unsigned long bist)
sdram_initialize(ARRAY_SIZE(mch), mch);
}
-#include "cpu/intel/model_6fx/cache_as_ram_disable.c"
+/* Use Intel Core (not Core 2) code for CAR init, any CPU might be used. */
+#include "cpu/intel/model_6ex/cache_as_ram_disable.c"