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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-11-18 18:52:04 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-11-20 21:22:25 +0100
commitfc5d85cc66046b239fdd45ff422d70146da1030c (patch)
tree29d21977647671706f448ad4ee2f9674dc18c920 /src
parent7dc4b84d8c61f233cb33f2adb7962f2f8a95badb (diff)
downloadcoreboot-fc5d85cc66046b239fdd45ff422d70146da1030c.tar.xz
intel sandy/ivy: Change CRC used to detect DIMM replacement
Switch to use CRC of unique identifier section SPD[117..127], remaining area of SPD data is ignored. Change-Id: If4b43183f99f5f911ae6c311b43c29a72b9922e2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17487 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src')
-rw-r--r--src/northbridge/intel/sandybridge/raminit.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 0842d4bf93..6ae253dbfe 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -355,7 +355,7 @@ static int verify_crc16_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl)
for (slot = 0; slot < NUM_SLOTS; slot++) {
spd_slot = 2 * channel + slot;
match &= ctrl->spd_crc[channel][slot] ==
- spd_ddr3_calc_crc(spd[spd_slot], sizeof(spd_raw_data));
+ spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data));
}
}
return match;
@@ -415,7 +415,7 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl)
/* fill in CRC16 for MRC cache */
ctrl->spd_crc[channel][slot] =
- spd_ddr3_calc_crc(spd[spd_slot], sizeof(spd_raw_data));
+ spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data));
if (dimm->dimm[channel][slot].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) {
// set dimm invalid