diff options
author | Shelley Chen <shchen@google.com> | 2019-01-25 14:44:42 -0800 |
---|---|---|
committer | Furquan Shaikh <furquan@google.com> | 2019-01-30 06:32:23 +0000 |
commit | fced3fe170c698231a35b83e4b13538ef08981a8 (patch) | |
tree | ee9206268b6a029b3df7692aada484776059302d /src | |
parent | e81f334c5948f508bd91431e51f26249257e8c15 (diff) | |
download | coreboot-fced3fe170c698231a35b83e4b13538ef08981a8.tar.xz |
mb/google/hatch: Enable AP Wake from EC
Initialize EC_PCH_WAKE_ODL GPIO to make sure that ec events will wake
the AP from suspend. Also create a task to initialize the hostevent
wake mask properly.
BUG=b:123325238,b:123325720
BRANCH=None
TEST=from AP console: powerd_dbus_suspend
from EC console: hostevent (make sure wake mask set)
from EC console: gpioset PCH_WAKE_L 0
Make sure device wakes up
Also, checked to make sure keyboard press wakes up
device from S3.
Change-Id: I53d5291a6b9ab9a21e89ccd21f172180ce473bd5
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/31100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
-rw-r--r-- | src/mainboard/google/hatch/Makefile.inc | 1 | ||||
-rw-r--r-- | src/mainboard/google/hatch/ec.c | 32 | ||||
-rw-r--r-- | src/mainboard/google/hatch/ramstage.c | 3 | ||||
-rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 6 | ||||
-rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/gpio.c | 3 | ||||
-rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h | 2 |
6 files changed, 46 insertions, 1 deletions
diff --git a/src/mainboard/google/hatch/Makefile.inc b/src/mainboard/google/hatch/Makefile.inc index ca8c7f2b76..3f35f8266e 100644 --- a/src/mainboard/google/hatch/Makefile.inc +++ b/src/mainboard/google/hatch/Makefile.inc @@ -18,6 +18,7 @@ bootblock-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += ramstage.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c romstage-y += romstage.c romstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/hatch/ec.c b/src/mainboard/google/hatch/ec.c new file mode 100644 index 0000000000..9fb3d80195 --- /dev/null +++ b/src/mainboard/google/hatch/ec.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <ec/ec.h> +#include <ec/google/chromeec/ec.h> +#include <variant/ec.h> + +void mainboard_ec_init(void) +{ + const struct google_chromeec_event_info info = { + .log_events = MAINBOARD_EC_LOG_EVENTS, + .sci_events = MAINBOARD_EC_SCI_EVENTS, + .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, + .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, + .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS, + }; + + google_chromeec_events_init(&info, acpi_is_wakeup_s3()); +} diff --git a/src/mainboard/google/hatch/ramstage.c b/src/mainboard/google/hatch/ramstage.c index d139effef2..b8e80e744a 100644 --- a/src/mainboard/google/hatch/ramstage.c +++ b/src/mainboard/google/hatch/ramstage.c @@ -15,6 +15,7 @@ #include <arch/acpi.h> #include <baseboard/variants.h> +#include <ec/ec.h> #include <soc/ramstage.h> #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -30,6 +31,8 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) static void mainboard_enable(struct device *dev) { + mainboard_ec_init(); + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; } diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 30a282b4b9..cea64e4237 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -250,7 +250,11 @@ chip soc/intel/cannonlake end end # GSPI #0 device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on end # LPC/eSPI + device pci 1f.0 on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # eSPI Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller device pci 1f.3 off end # Intel HDA diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index ade9ed21d7..a078997426 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -143,6 +143,9 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* SD_WP => NC */ PAD_NC(GPP_G7, DN_20K), + + /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_OD */ + PAD_CFG_NF(GPD2, NONE, DEEP, NF1), }; const struct pad_config *__weak variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h index c60699e6da..f9cebd7a38 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h @@ -52,6 +52,8 @@ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) +#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) + /* Log EC wake events plus EC shutdown events */ #define MAINBOARD_EC_LOG_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ |