diff options
| author | Myles Watson <mylesgw@gmail.com> | 2009-05-11 22:44:14 +0000 |
|---|---|---|
| committer | Myles Watson <mylesgw@gmail.com> | 2009-05-11 22:44:14 +0000 |
| commit | 0520d55f5b20ed0b5f192a695aff033320875233 (patch) | |
| tree | 23987377fd54be164ff3195487abb2fc14caba5e /src | |
| parent | 032a9653a6d5e1c61221358979a45852739ff379 (diff) | |
| download | coreboot-0520d55f5b20ed0b5f192a695aff033320875233.tar.xz | |
This patch adds high table support to qemu. It was already added to
src/northbridge/intel/i440bx/ but not to
src/cpu/emulation/qemu-x86/northbridge.c
It also adds a driver for the ISA device that is found when using
0.9.1 If you look in a log without this patch you won't find the RTC
init lines.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4269 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/emulation/qemu-x86/northbridge.c | 14 | ||||
| -rw-r--r-- | src/mainboard/emulation/qemu-x86/Options.lb | 3 | ||||
| -rw-r--r-- | src/southbridge/intel/i82371eb/i82371eb_isa.c | 6 |
3 files changed, 22 insertions, 1 deletions
diff --git a/src/cpu/emulation/qemu-x86/northbridge.c b/src/cpu/emulation/qemu-x86/northbridge.c index f9b63ca848..34745a0f57 100644 --- a/src/cpu/emulation/qemu-x86/northbridge.c +++ b/src/cpu/emulation/qemu-x86/northbridge.c @@ -65,6 +65,11 @@ static uint32_t find_pci_tolm(struct bus *bus) return tolm; } +#if HAVE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif + static void pci_domain_set_resources(device_t dev) { static const uint8_t ramregs[] = { @@ -110,7 +115,14 @@ static void pci_domain_set_resources(device_t dev) /* Report the memory regions. */ idx = 10; - ram_resource(dev, idx++, 0, tolmk); + ram_resource(dev, idx++, 0, 640); + ram_resource(dev, idx++, 768, tolmk - 768); + +#if HAVE_HIGH_TABLES==1 + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; +#endif } assign_resources(&dev->link[0]); } diff --git a/src/mainboard/emulation/qemu-x86/Options.lb b/src/mainboard/emulation/qemu-x86/Options.lb index 70d127c1a3..be26befdcc 100644 --- a/src/mainboard/emulation/qemu-x86/Options.lb +++ b/src/mainboard/emulation/qemu-x86/Options.lb @@ -31,6 +31,7 @@ uses _RAMBASE uses XIP_ROM_SIZE uses XIP_ROM_BASE uses HAVE_MP_TABLE +uses HAVE_HIGH_TABLES uses CROSS_COMPILE uses CC uses HOSTCC @@ -80,6 +81,8 @@ default HAVE_HARD_RESET=0 default HAVE_PIRQ_TABLE=1 default IRQ_SLOT_COUNT=6 +default HAVE_HIGH_TABLES=1 + ## ## Build code to export a CMOS option table ## diff --git a/src/southbridge/intel/i82371eb/i82371eb_isa.c b/src/southbridge/intel/i82371eb/i82371eb_isa.c index 95a706df77..dcfa16211a 100644 --- a/src/southbridge/intel/i82371eb/i82371eb_isa.c +++ b/src/southbridge/intel/i82371eb/i82371eb_isa.c @@ -70,3 +70,9 @@ static const struct pci_driver isa_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82371AB_ISA, }; + +static const struct pci_driver isa_SB_driver __pci_driver = { + .ops = &isa_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371SB_ISA, +}; |