diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-06-17 23:37:49 +0300 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-30 09:19:10 +0000 |
| commit | 0c1dd9c84188cc150a05302cc9b4af476a761d2b (patch) | |
| tree | cf8249cc3ba689e903c64d926c162c1e1f742d78 /src | |
| parent | bc1cb38ce15e059988263b04c0ea751ddf4b052d (diff) | |
| download | coreboot-0c1dd9c84188cc150a05302cc9b4af476a761d2b.tar.xz | |
ACPI: Drop typedef global_nvs_t
Bring all GNVS related initialisation function to global
scope to force identical signatures. Followup work is
likely to remove some as duplicates.
Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
188 files changed, 401 insertions, 318 deletions
diff --git a/src/include/acpi/acpi_gnvs.h b/src/include/acpi/acpi_gnvs.h index cc0c4710ae..6173fa168b 100644 --- a/src/include/acpi/acpi_gnvs.h +++ b/src/include/acpi/acpi_gnvs.h @@ -16,4 +16,21 @@ size_t gnvs_size_of_array(void); uint32_t *gnvs_cbmc_ptr(void); void *gnvs_chromeos_ptr(void); +/* + * Creates acpi gnvs and adds it to the DSDT table. + * GNVS creation is chipset specific and is done in soc specific acpi.c file. + */ +struct device; +void southbridge_inject_dsdt(const struct device *device); + +/* + * This function populates the gnvs structure in acpi table. + * Defined as weak in common acpi as gnvs structure definition is + * chipset specific. + */ +struct global_nvs; + +void acpi_create_gnvs(struct global_nvs *gnvs); +void acpi_init_gnvs(struct global_nvs *gnvs); + #endif diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index cdc690178a..56352c5d6f 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -86,6 +86,7 @@ struct smm_module_params { typedef asmlinkage void (*smm_handler_t)(void *); /* SMM Runtime helpers. */ +struct global_nvs *smm_get_gnvs(void); /* Entry point for SMM modules. */ asmlinkage void smm_handler_start(void *params); diff --git a/src/mainboard/apple/macbook21/acpi_tables.c b/src/mainboard/apple/macbook21/acpi_tables.c index 39ccb0194b..52c2fbbec1 100644 --- a/src/mainboard/apple/macbook21/acpi_tables.c +++ b/src/mainboard/apple/macbook21/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/i82801gx/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* Enable both COM ports */ gnvs->cmap = 0x01; diff --git a/src/mainboard/apple/macbookair4_2/gnvs.c b/src/mainboard/apple/macbookair4_2/gnvs.c index 55f9eb20cd..846f0797bc 100644 --- a/src/mainboard/apple/macbookair4_2/gnvs.c +++ b/src/mainboard/apple/macbookair4_2/gnvs.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* Disable USB ports in S3 by default */ gnvs->s3u0 = 0; diff --git a/src/mainboard/asrock/b75pro3-m/acpi_tables.c b/src/mainboard/asrock/b75pro3-m/acpi_tables.c index 33feed2a98..28c9d8ee6e 100644 --- a/src/mainboard/asrock/b75pro3-m/acpi_tables.c +++ b/src/mainboard/asrock/b75pro3-m/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = 100; gnvs->tpsv = 90; diff --git a/src/mainboard/asrock/b85m_pro4/acpi_tables.c b/src/mainboard/asrock/b85m_pro4/acpi_tables.c index f00b3e70f1..eed290d500 100644 --- a/src/mainboard/asrock/b85m_pro4/acpi_tables.c +++ b/src/mainboard/asrock/b85m_pro4/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/lynxpoint/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = 100; gnvs->tpsv = 90; diff --git a/src/mainboard/asrock/g41c-gs/acpi_tables.c b/src/mainboard/asrock/g41c-gs/acpi_tables.c index ec9420c25a..9eef15936a 100644 --- a/src/mainboard/asrock/g41c-gs/acpi_tables.c +++ b/src/mainboard/asrock/g41c-gs/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/i82801gx/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ gnvs->cmap = 0x01; /* Enable COM 1 port */ diff --git a/src/mainboard/asrock/h81m-hds/acpi_tables.c b/src/mainboard/asrock/h81m-hds/acpi_tables.c index 3bc934043c..8ec5b118c5 100644 --- a/src/mainboard/asrock/h81m-hds/acpi_tables.c +++ b/src/mainboard/asrock/h81m-hds/acpi_tables.c @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/lynxpoint/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { } diff --git a/src/mainboard/asus/h61m-cs/acpi_tables.c b/src/mainboard/asus/h61m-cs/acpi_tables.c index 47cf3c2dc2..852b0b4ae7 100644 --- a/src/mainboard/asus/h61m-cs/acpi_tables.c +++ b/src/mainboard/asus/h61m-cs/acpi_tables.c @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { } diff --git a/src/mainboard/asus/maximus_iv_gene-z/acpi_tables.c b/src/mainboard/asus/maximus_iv_gene-z/acpi_tables.c index 1dd16ab5ac..14a79f87fb 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/acpi_tables.c +++ b/src/mainboard/asus/maximus_iv_gene-z/acpi_tables.c @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { } diff --git a/src/mainboard/asus/p5gc-mx/acpi_tables.c b/src/mainboard/asus/p5gc-mx/acpi_tables.c index 558346229d..496d4190c6 100644 --- a/src/mainboard/asus/p5gc-mx/acpi_tables.c +++ b/src/mainboard/asus/p5gc-mx/acpi_tables.c @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/i82801gx/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { } diff --git a/src/mainboard/asus/p5qc/acpi_tables.c b/src/mainboard/asus/p5qc/acpi_tables.c index 8b1303e6fe..65db55f5cb 100644 --- a/src/mainboard/asus/p5qc/acpi_tables.c +++ b/src/mainboard/asus/p5qc/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/i82801jx/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ diff --git a/src/mainboard/asus/p5ql-em/acpi_tables.c b/src/mainboard/asus/p5ql-em/acpi_tables.c index b65ca71789..4f59ed01f8 100644 --- a/src/mainboard/asus/p5ql-em/acpi_tables.c +++ b/src/mainboard/asus/p5ql-em/acpi_tables.c @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpigen.h> +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/i82801jx/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ diff --git a/src/mainboard/asus/p5qpl-am/acpi_tables.c b/src/mainboard/asus/p5qpl-am/acpi_tables.c index ec9420c25a..9eef15936a 100644 --- a/src/mainboard/asus/p5qpl-am/acpi_tables.c +++ b/src/mainboard/asus/p5qpl-am/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/i82801gx/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ gnvs->cmap = 0x01; /* Enable COM 1 port */ diff --git a/src/mainboard/asus/p8h61-m_lx/acpi_tables.c b/src/mainboard/asus/p8h61-m_lx/acpi_tables.c index 1dd16ab5ac..14a79f87fb 100644 --- a/src/mainboard/asus/p8h61-m_lx/acpi_tables.c +++ b/src/mainboard/asus/p8h61-m_lx/acpi_tables.c @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { } diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c index 33feed2a98..28c9d8ee6e 100644 --- a/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = 100; gnvs->tpsv = 90; diff --git a/src/mainboard/asus/p8h61-m_pro/acpi_tables.c b/src/mainboard/asus/p8h61-m_pro/acpi_tables.c index 33feed2a98..28c9d8ee6e 100644 --- a/src/mainboard/asus/p8h61-m_pro/acpi_tables.c +++ b/src/mainboard/asus/p8h61-m_pro/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = 100; gnvs->tpsv = 90; diff --git a/src/mainboard/asus/p8z77-m_pro/acpi_tables.c b/src/mainboard/asus/p8z77-m_pro/acpi_tables.c index 6c1b4da0c3..e401b656fa 100644 --- a/src/mainboard/asus/p8z77-m_pro/acpi_tables.c +++ b/src/mainboard/asus/p8z77-m_pro/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* critical temp that will shutdown the pc == 95C degrees */ gnvs->tcrt = 95; diff --git a/src/mainboard/asus/p8z77-v_lx2/acpi_tables.c b/src/mainboard/asus/p8z77-v_lx2/acpi_tables.c index 33feed2a98..28c9d8ee6e 100644 --- a/src/mainboard/asus/p8z77-v_lx2/acpi_tables.c +++ b/src/mainboard/asus/p8z77-v_lx2/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = 100; gnvs->tpsv = 90; diff --git a/src/mainboard/compulab/intense_pc/acpi_tables.c b/src/mainboard/compulab/intense_pc/acpi_tables.c index 126708cca8..f9051870d6 100644 --- a/src/mainboard/compulab/intense_pc/acpi_tables.c +++ b/src/mainboard/compulab/intense_pc/acpi_tables.c @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> /* FIXME: check this function. */ -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = 100; gnvs->tpsv = 90; diff --git a/src/mainboard/dell/optiplex_9010/acpi_tables.c b/src/mainboard/dell/optiplex_9010/acpi_tables.c index 33feed2a98..28c9d8ee6e 100644 --- a/src/mainboard/dell/optiplex_9010/acpi_tables.c +++ b/src/mainboard/dell/optiplex_9010/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = 100; gnvs->tpsv = 90; diff --git a/src/mainboard/emulation/qemu-q35/acpi_tables.c b/src/mainboard/emulation/qemu-q35/acpi_tables.c index d3492f7b51..51baae5135 100644 --- a/src/mainboard/emulation/qemu-q35/acpi_tables.c +++ b/src/mainboard/emulation/qemu-q35/acpi_tables.c @@ -3,6 +3,7 @@ #include <types.h> #include <string.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> #include <device/device.h> @@ -13,7 +14,7 @@ #include "../qemu-i440fx/acpi.h" #include <southbridge/intel/i82801ix/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { gnvs->apic = 1; gnvs->mpen = 1; /* Enable Multi Processing */ diff --git a/src/mainboard/facebook/fbg1701/acpi_tables.c b/src/mainboard/facebook/fbg1701/acpi_tables.c index e98df1460d..5fe4a4260e 100644 --- a/src/mainboard/facebook/fbg1701/acpi_tables.c +++ b/src/mainboard/facebook/fbg1701/acpi_tables.c @@ -1,11 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <arch/ioapic.h> #include <soc/acpi.h> #include <soc/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { acpi_init_gnvs(gnvs); diff --git a/src/mainboard/foxconn/d41s/acpi_tables.c b/src/mainboard/foxconn/d41s/acpi_tables.c index 558346229d..496d4190c6 100644 --- a/src/mainboard/foxconn/d41s/acpi_tables.c +++ b/src/mainboard/foxconn/d41s/acpi_tables.c @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/i82801gx/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { } diff --git a/src/mainboard/foxconn/g41s-k/acpi_tables.c b/src/mainboard/foxconn/g41s-k/acpi_tables.c index 65805056dc..781abcce7e 100644 --- a/src/mainboard/foxconn/g41s-k/acpi_tables.c +++ b/src/mainboard/foxconn/g41s-k/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/i82801gx/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ gnvs->cmap = 1; /* COM 1 port */ diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c index 3abf8aa388..d555c100a0 100644 --- a/src/mainboard/getac/p470/acpi_tables.c +++ b/src/mainboard/getac/p470/acpi_tables.c @@ -4,12 +4,13 @@ #include <string.h> #include <console/console.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <device/device.h> #include <southbridge/intel/i82801gx/nvs.h> #include "mainboard.h" -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* Enable COM port(s) */ gnvs->cmap = 0x01; diff --git a/src/mainboard/getac/p470/smihandler.c b/src/mainboard/getac/p470/smihandler.c index 4172e9450c..145c942b0c 100644 --- a/src/mainboard/getac/p470/smihandler.c +++ b/src/mainboard/getac/p470/smihandler.c @@ -14,7 +14,7 @@ /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ -extern global_nvs_t *gnvs; +extern struct global_nvs *gnvs; int mainboard_io_trap_handler(int smif) { diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi_tables.c b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi_tables.c index 558346229d..496d4190c6 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi_tables.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi_tables.c @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/i82801gx/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { } diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c index a889b9f737..3012052a24 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> #include "thermal.h" -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = CRITICAL_TEMPERATURE; gnvs->tpsv = PASSIVE_TEMPERATURE; diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c b/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c index 68d0e8e531..f7296e14f2 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/i82801gx/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ gnvs->lptp = 0; /* LPT port */ diff --git a/src/mainboard/gigabyte/ga-h61m-series/acpi_tables.c b/src/mainboard/gigabyte/ga-h61m-series/acpi_tables.c index 47cf3c2dc2..852b0b4ae7 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/acpi_tables.c +++ b/src/mainboard/gigabyte/ga-h61m-series/acpi_tables.c @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { } diff --git a/src/mainboard/google/auron/acpi_tables.c b/src/mainboard/google/auron/acpi_tables.c index 4c72f3e0e6..10dc637f01 100644 --- a/src/mainboard/google/auron/acpi_tables.c +++ b/src/mainboard/google/auron/acpi_tables.c @@ -2,11 +2,12 @@ #include <arch/ioapic.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <soc/acpi.h> #include <soc/nvs.h> #include <variant/thermal.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { acpi_init_gnvs(gnvs); diff --git a/src/mainboard/google/beltino/acpi_tables.c b/src/mainboard/google/beltino/acpi_tables.c index d2f7f45ff1..a34a1e9a63 100644 --- a/src/mainboard/google/beltino/acpi_tables.c +++ b/src/mainboard/google/beltino/acpi_tables.c @@ -2,6 +2,7 @@ #include <types.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <device/device.h> #include <ec/google/chromeec/ec.h> #include <southbridge/intel/lynxpoint/nvs.h> @@ -9,7 +10,7 @@ #include <vendorcode/google/chromeos/gnvs.h> #include <variant/thermal.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* Enable USB ports in S3 */ gnvs->s3u0 = 1; diff --git a/src/mainboard/google/butterfly/acpi_tables.c b/src/mainboard/google/butterfly/acpi_tables.c index 9680e8f489..7ac37b2d46 100644 --- a/src/mainboard/google/butterfly/acpi_tables.c +++ b/src/mainboard/google/butterfly/acpi_tables.c @@ -1,10 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> #include <vendorcode/google/chromeos/gnvs.h> #include "thermal.h" -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* Disable USB ports in S3 by default */ gnvs->s3u0 = 0; diff --git a/src/mainboard/google/butterfly/mainboard_smi.c b/src/mainboard/google/butterfly/mainboard_smi.c index d4f2b99017..4d5bc4f9be 100644 --- a/src/mainboard/google/butterfly/mainboard_smi.c +++ b/src/mainboard/google/butterfly/mainboard_smi.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <southbridge/intel/bd82x6x/nvs.h> diff --git a/src/mainboard/google/cyan/acpi_tables.c b/src/mainboard/google/cyan/acpi_tables.c index a99c4131a9..2f2f298f8e 100644 --- a/src/mainboard/google/cyan/acpi_tables.c +++ b/src/mainboard/google/cyan/acpi_tables.c @@ -1,11 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <arch/ioapic.h> #include <soc/acpi.h> #include <soc/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { acpi_init_gnvs(gnvs); diff --git a/src/mainboard/google/jecht/acpi_tables.c b/src/mainboard/google/jecht/acpi_tables.c index c566d844ef..1b96df6327 100644 --- a/src/mainboard/google/jecht/acpi_tables.c +++ b/src/mainboard/google/jecht/acpi_tables.c @@ -2,13 +2,14 @@ #include <types.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <arch/ioapic.h> #include <device/device.h> #include <soc/acpi.h> #include <soc/nvs.h> #include <variant/thermal.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { acpi_init_gnvs(gnvs); diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index 5e1bdf4c2d..d67cdec6fd 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -163,7 +163,7 @@ static void kahlee_enable(struct device *dev) static void mainboard_final(void *chip_info) { - struct global_nvs_t *gnvs; + struct global_nvs *gnvs; gnvs = acpi_get_gnvs(); diff --git a/src/mainboard/google/link/acpi_tables.c b/src/mainboard/google/link/acpi_tables.c index 36b635e657..f37f37e6cf 100644 --- a/src/mainboard/google/link/acpi_tables.c +++ b/src/mainboard/google/link/acpi_tables.c @@ -1,11 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> #include <ec/google/chromeec/ec.h> #include <vendorcode/google/chromeos/gnvs.h> #include "thermal.h" -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* Disable USB ports in S3 by default */ gnvs->s3u0 = 0; diff --git a/src/mainboard/google/link/mainboard_smi.c b/src/mainboard/google/link/mainboard_smi.c index e7ec33289d..e60ceae649 100644 --- a/src/mainboard/google/link/mainboard_smi.c +++ b/src/mainboard/google/link/mainboard_smi.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <southbridge/intel/bd82x6x/nvs.h> diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c index 62722ec486..a4d33198df 100644 --- a/src/mainboard/google/parrot/acpi_tables.c +++ b/src/mainboard/google/parrot/acpi_tables.c @@ -2,6 +2,7 @@ #include <types.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <device/device.h> #include <vendorcode/google/chromeos/gnvs.h> #include <ec/compal/ene932/ec.h> @@ -12,7 +13,7 @@ #include "thermal.h" #include "onboard.h" -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* Disable USB ports in S3 by default */ gnvs->s3u0 = 0; diff --git a/src/mainboard/google/rambi/acpi_tables.c b/src/mainboard/google/rambi/acpi_tables.c index c336d53d23..54735cec4c 100644 --- a/src/mainboard/google/rambi/acpi_tables.c +++ b/src/mainboard/google/rambi/acpi_tables.c @@ -2,13 +2,14 @@ #include <types.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <arch/ioapic.h> #include <device/device.h> #include <soc/acpi.h> #include <soc/nvs.h> #include <soc/iomap.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { acpi_init_gnvs(gnvs); diff --git a/src/mainboard/google/rambi/mainboard_smi.c b/src/mainboard/google/rambi/mainboard_smi.c index f68a2c3e45..e6e40aa7fd 100644 --- a/src/mainboard/google/rambi/mainboard_smi.c +++ b/src/mainboard/google/rambi/mainboard_smi.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c index ba55647e03..28364c9b1a 100644 --- a/src/mainboard/google/slippy/acpi_tables.c +++ b/src/mainboard/google/slippy/acpi_tables.c @@ -2,6 +2,7 @@ #include <types.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <device/device.h> #include <vendorcode/google/chromeos/gnvs.h> #include <ec/google/chromeec/ec.h> @@ -10,7 +11,7 @@ #include "thermal.h" -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* Enable USB ports in S3 */ gnvs->s3u0 = 1; diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c index 08bd4cdd1c..101e8f118a 100644 --- a/src/mainboard/google/stout/acpi_tables.c +++ b/src/mainboard/google/stout/acpi_tables.c @@ -2,6 +2,7 @@ #include <types.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <device/device.h> #include <vendorcode/google/chromeos/gnvs.h> #include <bootmode.h> @@ -13,7 +14,7 @@ #include <southbridge/intel/bd82x6x/nvs.h> #include "thermal.h" -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* Disable USB ports in S3 by default */ gnvs->s3u0 = 0; diff --git a/src/mainboard/google/stout/mainboard_smi.c b/src/mainboard/google/stout/mainboard_smi.c index cf7fcaea65..0b6b227707 100644 --- a/src/mainboard/google/stout/mainboard_smi.c +++ b/src/mainboard/google/stout/mainboard_smi.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <device/pci_ops.h> #include <console/console.h> #include <cpu/x86/smm.h> diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c index 1ed3e9d0f8..283f0e0841 100644 --- a/src/mainboard/google/zork/mainboard.c +++ b/src/mainboard/google/zork/mainboard.c @@ -194,7 +194,7 @@ static void reset_backlight_gpio(void *unused) static void mainboard_final(void *chip_info) { - struct global_nvs_t *gnvs; + struct global_nvs *gnvs; gnvs = acpi_get_gnvs(); diff --git a/src/mainboard/hp/compaq_8200_elite_sff/acpi_tables.c b/src/mainboard/hp/compaq_8200_elite_sff/acpi_tables.c index 33feed2a98..28c9d8ee6e 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/acpi_tables.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = 100; gnvs->tpsv = 90; diff --git a/src/mainboard/hp/snb_ivb_laptops/acpi_tables.c b/src/mainboard/hp/snb_ivb_laptops/acpi_tables.c index 0ef356657d..8999b7297c 100644 --- a/src/mainboard/hp/snb_ivb_laptops/acpi_tables.c +++ b/src/mainboard/hp/snb_ivb_laptops/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { // the lid is open by default. gnvs->lids = 1; diff --git a/src/mainboard/hp/z220_sff_workstation/acpi_tables.c b/src/mainboard/hp/z220_sff_workstation/acpi_tables.c index 33feed2a98..28c9d8ee6e 100644 --- a/src/mainboard/hp/z220_sff_workstation/acpi_tables.c +++ b/src/mainboard/hp/z220_sff_workstation/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = 100; gnvs->tpsv = 90; diff --git a/src/mainboard/ibase/mb899/acpi_tables.c b/src/mainboard/ibase/mb899/acpi_tables.c index 39ccb0194b..52c2fbbec1 100644 --- a/src/mainboard/ibase/mb899/acpi_tables.c +++ b/src/mainboard/ibase/mb899/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/i82801gx/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* Enable both COM ports */ gnvs->cmap = 0x01; diff --git a/src/mainboard/intel/baskingridge/acpi_tables.c b/src/mainboard/intel/baskingridge/acpi_tables.c index 24edfea49f..d31735d3df 100644 --- a/src/mainboard/intel/baskingridge/acpi_tables.c +++ b/src/mainboard/intel/baskingridge/acpi_tables.c @@ -2,6 +2,7 @@ #include <types.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <device/device.h> #include <vendorcode/google/chromeos/gnvs.h> #include <southbridge/intel/lynxpoint/pch.h> @@ -9,7 +10,7 @@ #include "thermal.h" -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* Enable USB ports in S3 */ gnvs->s3u0 = 1; diff --git a/src/mainboard/intel/d510mo/acpi_tables.c b/src/mainboard/intel/d510mo/acpi_tables.c index 558346229d..496d4190c6 100644 --- a/src/mainboard/intel/d510mo/acpi_tables.c +++ b/src/mainboard/intel/d510mo/acpi_tables.c @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/i82801gx/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { } diff --git a/src/mainboard/intel/d945gclf/acpi_tables.c b/src/mainboard/intel/d945gclf/acpi_tables.c index 558346229d..496d4190c6 100644 --- a/src/mainboard/intel/d945gclf/acpi_tables.c +++ b/src/mainboard/intel/d945gclf/acpi_tables.c @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/i82801gx/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { } diff --git a/src/mainboard/intel/dcp847ske/acpi_tables.c b/src/mainboard/intel/dcp847ske/acpi_tables.c index 6078e678f3..43e5062bb8 100644 --- a/src/mainboard/intel/dcp847ske/acpi_tables.c +++ b/src/mainboard/intel/dcp847ske/acpi_tables.c @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> #include "thermal.h" -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* Enable USB ports in S3 by default */ gnvs->s3u0 = 1; diff --git a/src/mainboard/intel/dg41wv/acpi_tables.c b/src/mainboard/intel/dg41wv/acpi_tables.c index ec9420c25a..9eef15936a 100644 --- a/src/mainboard/intel/dg41wv/acpi_tables.c +++ b/src/mainboard/intel/dg41wv/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/i82801gx/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ gnvs->cmap = 0x01; /* Enable COM 1 port */ diff --git a/src/mainboard/intel/dg43gt/acpi_tables.c b/src/mainboard/intel/dg43gt/acpi_tables.c index 8b1303e6fe..65db55f5cb 100644 --- a/src/mainboard/intel/dg43gt/acpi_tables.c +++ b/src/mainboard/intel/dg43gt/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/i82801jx/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ diff --git a/src/mainboard/intel/emeraldlake2/acpi_tables.c b/src/mainboard/intel/emeraldlake2/acpi_tables.c index dd98883ff6..2ae7de4162 100644 --- a/src/mainboard/intel/emeraldlake2/acpi_tables.c +++ b/src/mainboard/intel/emeraldlake2/acpi_tables.c @@ -2,13 +2,14 @@ #include <types.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <device/device.h> #include <vendorcode/google/chromeos/gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> #include "thermal.h" -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* Enable USB ports in S3 */ gnvs->s3u0 = 1; diff --git a/src/mainboard/intel/harcuvar/acpi_tables.c b/src/mainboard/intel/harcuvar/acpi_tables.c index b939a813a6..cfe0caa585 100644 --- a/src/mainboard/intel/harcuvar/acpi_tables.c +++ b/src/mainboard/intel/harcuvar/acpi_tables.c @@ -2,6 +2,7 @@ #include <types.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <device/device.h> #include <cpu/x86/msr.h> @@ -11,7 +12,7 @@ extern const unsigned char AmlCode[]; -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { acpi_init_gnvs(gnvs); diff --git a/src/mainboard/intel/strago/acpi_tables.c b/src/mainboard/intel/strago/acpi_tables.c index 8e26d3ce8f..2df0d15b21 100644 --- a/src/mainboard/intel/strago/acpi_tables.c +++ b/src/mainboard/intel/strago/acpi_tables.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <arch/ioapic.h> #include <device/device.h> #include <soc/acpi.h> @@ -10,7 +11,7 @@ #include <boardid.h> #include "onboard.h" -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { acpi_init_gnvs(gnvs); diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c index 5c7e13ed1b..416f945965 100644 --- a/src/mainboard/intel/wtm2/acpi_tables.c +++ b/src/mainboard/intel/wtm2/acpi_tables.c @@ -2,13 +2,14 @@ #include <types.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <arch/ioapic.h> #include <device/device.h> #include <soc/acpi.h> #include <soc/nvs.h> #include "thermal.h" -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { acpi_init_gnvs(gnvs); diff --git a/src/mainboard/kontron/986lcd-m/acpi_tables.c b/src/mainboard/kontron/986lcd-m/acpi_tables.c index 39ccb0194b..52c2fbbec1 100644 --- a/src/mainboard/kontron/986lcd-m/acpi_tables.c +++ b/src/mainboard/kontron/986lcd-m/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/i82801gx/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* Enable both COM ports */ gnvs->cmap = 0x01; diff --git a/src/mainboard/kontron/ktqm77/acpi_tables.c b/src/mainboard/kontron/ktqm77/acpi_tables.c index a889b9f737..3012052a24 100644 --- a/src/mainboard/kontron/ktqm77/acpi_tables.c +++ b/src/mainboard/kontron/ktqm77/acpi_tables.c @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> #include "thermal.h" -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = CRITICAL_TEMPERATURE; gnvs->tpsv = PASSIVE_TEMPERATURE; diff --git a/src/mainboard/lenovo/l520/acpi_tables.c b/src/mainboard/lenovo/l520/acpi_tables.c index 23086fcdd5..6f69102dbc 100644 --- a/src/mainboard/lenovo/l520/acpi_tables.c +++ b/src/mainboard/lenovo/l520/acpi_tables.c @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/s230u/acpi_tables.c b/src/mainboard/lenovo/s230u/acpi_tables.c index a0ad250487..0f32e9f90c 100644 --- a/src/mainboard/lenovo/s230u/acpi_tables.c +++ b/src/mainboard/lenovo/s230u/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t400/acpi_tables.c b/src/mainboard/lenovo/t400/acpi_tables.c index 91cf2c37ed..14b5a8bbe9 100644 --- a/src/mainboard/lenovo/t400/acpi_tables.c +++ b/src/mainboard/lenovo/t400/acpi_tables.c @@ -2,11 +2,12 @@ #include <arch/ioapic.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <arch/smp/mpspec.h> #include <device/device.h> #include <southbridge/intel/i82801ix/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { gnvs->apic = 1; gnvs->mpen = 1; /* Enable Multi Processing */ diff --git a/src/mainboard/lenovo/t410/acpi_tables.c b/src/mainboard/lenovo/t410/acpi_tables.c index 49ab9ef94a..f957656b51 100644 --- a/src/mainboard/lenovo/t410/acpi_tables.c +++ b/src/mainboard/lenovo/t410/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/ibexpeak/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t420/acpi_tables.c b/src/mainboard/lenovo/t420/acpi_tables.c index a0ad250487..0f32e9f90c 100644 --- a/src/mainboard/lenovo/t420/acpi_tables.c +++ b/src/mainboard/lenovo/t420/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t420s/acpi_tables.c b/src/mainboard/lenovo/t420s/acpi_tables.c index a0ad250487..0f32e9f90c 100644 --- a/src/mainboard/lenovo/t420s/acpi_tables.c +++ b/src/mainboard/lenovo/t420s/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t430/acpi_tables.c b/src/mainboard/lenovo/t430/acpi_tables.c index d91d8cdaae..5cb1fd38d5 100644 --- a/src/mainboard/lenovo/t430/acpi_tables.c +++ b/src/mainboard/lenovo/t430/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t430s/acpi_tables.c b/src/mainboard/lenovo/t430s/acpi_tables.c index a0ad250487..0f32e9f90c 100644 --- a/src/mainboard/lenovo/t430s/acpi_tables.c +++ b/src/mainboard/lenovo/t430s/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t440p/acpi_tables.c b/src/mainboard/lenovo/t440p/acpi_tables.c index 11998f1d2e..c235d1228a 100644 --- a/src/mainboard/lenovo/t440p/acpi_tables.c +++ b/src/mainboard/lenovo/t440p/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/lynxpoint/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* The lid is open by default. */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t520/acpi_tables.c b/src/mainboard/lenovo/t520/acpi_tables.c index a0ad250487..0f32e9f90c 100644 --- a/src/mainboard/lenovo/t520/acpi_tables.c +++ b/src/mainboard/lenovo/t520/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t530/acpi_tables.c b/src/mainboard/lenovo/t530/acpi_tables.c index a0ad250487..0f32e9f90c 100644 --- a/src/mainboard/lenovo/t530/acpi_tables.c +++ b/src/mainboard/lenovo/t530/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t60/acpi_tables.c b/src/mainboard/lenovo/t60/acpi_tables.c index 436141031a..62fcfe95e6 100644 --- a/src/mainboard/lenovo/t60/acpi_tables.c +++ b/src/mainboard/lenovo/t60/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/i82801gx/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* Enable both COM ports */ gnvs->cmap = 0x01; diff --git a/src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c b/src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c index ec9420c25a..9eef15936a 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c +++ b/src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/i82801gx/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ gnvs->cmap = 0x01; /* Enable COM 1 port */ diff --git a/src/mainboard/lenovo/x131e/acpi_tables.c b/src/mainboard/lenovo/x131e/acpi_tables.c index a0ad250487..0f32e9f90c 100644 --- a/src/mainboard/lenovo/x131e/acpi_tables.c +++ b/src/mainboard/lenovo/x131e/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c b/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c index a0ad250487..0f32e9f90c 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/x200/acpi_tables.c b/src/mainboard/lenovo/x200/acpi_tables.c index 91cf2c37ed..14b5a8bbe9 100644 --- a/src/mainboard/lenovo/x200/acpi_tables.c +++ b/src/mainboard/lenovo/x200/acpi_tables.c @@ -2,11 +2,12 @@ #include <arch/ioapic.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <arch/smp/mpspec.h> #include <device/device.h> #include <southbridge/intel/i82801ix/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { gnvs->apic = 1; gnvs->mpen = 1; /* Enable Multi Processing */ diff --git a/src/mainboard/lenovo/x201/acpi_tables.c b/src/mainboard/lenovo/x201/acpi_tables.c index 49ab9ef94a..f957656b51 100644 --- a/src/mainboard/lenovo/x201/acpi_tables.c +++ b/src/mainboard/lenovo/x201/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/ibexpeak/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/x220/acpi_tables.c b/src/mainboard/lenovo/x220/acpi_tables.c index a0ad250487..0f32e9f90c 100644 --- a/src/mainboard/lenovo/x220/acpi_tables.c +++ b/src/mainboard/lenovo/x220/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/x230/acpi_tables.c b/src/mainboard/lenovo/x230/acpi_tables.c index a0ad250487..0f32e9f90c 100644 --- a/src/mainboard/lenovo/x230/acpi_tables.c +++ b/src/mainboard/lenovo/x230/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/x60/acpi_tables.c b/src/mainboard/lenovo/x60/acpi_tables.c index 436141031a..62fcfe95e6 100644 --- a/src/mainboard/lenovo/x60/acpi_tables.c +++ b/src/mainboard/lenovo/x60/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/i82801gx/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* Enable both COM ports */ gnvs->cmap = 0x01; diff --git a/src/mainboard/msi/ms7707/acpi_tables.c b/src/mainboard/msi/ms7707/acpi_tables.c index 33feed2a98..28c9d8ee6e 100644 --- a/src/mainboard/msi/ms7707/acpi_tables.c +++ b/src/mainboard/msi/ms7707/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = 100; gnvs->tpsv = 90; diff --git a/src/mainboard/ocp/tiogapass/acpi_tables.c b/src/mainboard/ocp/tiogapass/acpi_tables.c index 85372e5606..f6947a20b8 100644 --- a/src/mainboard/ocp/tiogapass/acpi_tables.c +++ b/src/mainboard/ocp/tiogapass/acpi_tables.c @@ -1,11 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <intelblocks/acpi.h> #include <soc/acpi.h> extern const unsigned char AmlCode[]; -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { acpi_init_gnvs(gnvs); } diff --git a/src/mainboard/packardbell/ms2290/acpi_tables.c b/src/mainboard/packardbell/ms2290/acpi_tables.c index 4ecec38aba..17ed31edb4 100644 --- a/src/mainboard/packardbell/ms2290/acpi_tables.c +++ b/src/mainboard/packardbell/ms2290/acpi_tables.c @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/ibexpeak/nvs.h> -void acpi_create_gnvs(global_nvs_t * gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { } diff --git a/src/mainboard/portwell/m107/acpi_tables.c b/src/mainboard/portwell/m107/acpi_tables.c index e98df1460d..5fe4a4260e 100644 --- a/src/mainboard/portwell/m107/acpi_tables.c +++ b/src/mainboard/portwell/m107/acpi_tables.c @@ -1,11 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <arch/ioapic.h> #include <soc/acpi.h> #include <soc/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { acpi_init_gnvs(gnvs); diff --git a/src/mainboard/protectli/vault_bsw/acpi_tables.c b/src/mainboard/protectli/vault_bsw/acpi_tables.c index 1724c71aec..c40769af98 100644 --- a/src/mainboard/protectli/vault_bsw/acpi_tables.c +++ b/src/mainboard/protectli/vault_bsw/acpi_tables.c @@ -1,10 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpi_gnvs.h> #include <arch/ioapic.h> #include <soc/acpi.h> #include <string.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { memset(gnvs, 0, sizeof(*gnvs)); diff --git a/src/mainboard/purism/librem_bdw/acpi_tables.c b/src/mainboard/purism/librem_bdw/acpi_tables.c index 8383f63f66..ca6f64b089 100644 --- a/src/mainboard/purism/librem_bdw/acpi_tables.c +++ b/src/mainboard/purism/librem_bdw/acpi_tables.c @@ -1,11 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <arch/ioapic.h> #include <soc/acpi.h> #include <soc/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { acpi_init_gnvs(gnvs); } diff --git a/src/mainboard/roda/rk886ex/acpi_tables.c b/src/mainboard/roda/rk886ex/acpi_tables.c index 39ccb0194b..52c2fbbec1 100644 --- a/src/mainboard/roda/rk886ex/acpi_tables.c +++ b/src/mainboard/roda/rk886ex/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/i82801gx/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* Enable both COM ports */ gnvs->cmap = 0x01; diff --git a/src/mainboard/roda/rk9/acpi_tables.c b/src/mainboard/roda/rk9/acpi_tables.c index 7cc2468b05..b0e8993f11 100644 --- a/src/mainboard/roda/rk9/acpi_tables.c +++ b/src/mainboard/roda/rk9/acpi_tables.c @@ -2,11 +2,12 @@ #include <arch/ioapic.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <arch/smp/mpspec.h> #include <device/device.h> #include <southbridge/intel/i82801ix/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { gnvs->apic = 1; gnvs->mpen = 1; /* Enable Multi Processing */ diff --git a/src/mainboard/roda/rv11/acpi_tables.c b/src/mainboard/roda/rv11/acpi_tables.c index 7477796a91..aea50a1774 100644 --- a/src/mainboard/roda/rv11/acpi_tables.c +++ b/src/mainboard/roda/rv11/acpi_tables.c @@ -1,10 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> #include <variant/thermal.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c index c1489eb7fd..e730bc2eba 100644 --- a/src/mainboard/samsung/lumpy/acpi_tables.c +++ b/src/mainboard/samsung/lumpy/acpi_tables.c @@ -2,6 +2,7 @@ #include <types.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <device/device.h> #include <ec/acpi/ec.h> #if CONFIG(CHROMEOS) @@ -11,7 +12,7 @@ #include "thermal.h" -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* * Disable 3G in suspend by default. diff --git a/src/mainboard/samsung/stumpy/acpi_tables.c b/src/mainboard/samsung/stumpy/acpi_tables.c index 9793c1cf94..dcdd4e5c3e 100644 --- a/src/mainboard/samsung/stumpy/acpi_tables.c +++ b/src/mainboard/samsung/stumpy/acpi_tables.c @@ -2,13 +2,14 @@ #include <types.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <device/device.h> #include <vendorcode/google/chromeos/gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> #include "thermal.h" -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* Enable Front USB ports in S3 by default */ gnvs->s3u0 = 1; diff --git a/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c b/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c index d20cbdb9d7..ccbb75ca14 100644 --- a/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c +++ b/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = 100; gnvs->tpsv = 90; diff --git a/src/mainboard/scaleway/tagada/acpi_tables.c b/src/mainboard/scaleway/tagada/acpi_tables.c index b939a813a6..cfe0caa585 100644 --- a/src/mainboard/scaleway/tagada/acpi_tables.c +++ b/src/mainboard/scaleway/tagada/acpi_tables.c @@ -2,6 +2,7 @@ #include <types.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <device/device.h> #include <cpu/x86/msr.h> @@ -11,7 +12,7 @@ extern const unsigned char AmlCode[]; -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { acpi_init_gnvs(gnvs); diff --git a/src/mainboard/supermicro/x10slm-f/acpi_tables.c b/src/mainboard/supermicro/x10slm-f/acpi_tables.c index 3bc934043c..8ec5b118c5 100644 --- a/src/mainboard/supermicro/x10slm-f/acpi_tables.c +++ b/src/mainboard/supermicro/x10slm-f/acpi_tables.c @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/lynxpoint/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { } diff --git a/src/mainboard/supermicro/x9scl/acpi_tables.c b/src/mainboard/supermicro/x9scl/acpi_tables.c index 33feed2a98..28c9d8ee6e 100644 --- a/src/mainboard/supermicro/x9scl/acpi_tables.c +++ b/src/mainboard/supermicro/x9scl/acpi_tables.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> -void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = 100; gnvs->tpsv = 90; diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 3ddedcebe8..5e18aad0bb 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <cbmem.h> #include <console/console.h> #include <device/device.h> @@ -91,7 +92,7 @@ static void lpc_init(struct device *dev) static void lpc_read_resources(struct device *dev) { struct resource *res; - global_nvs_t *gnvs; + struct global_nvs *gnvs; /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); @@ -127,7 +128,7 @@ static void lpc_read_resources(struct device *dev) compact_resources(dev); /* Allocate ACPI NVS in CBMEM */ - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs)); printk(BIOS_DEBUG, "ACPI GNVS at %p\n", gnvs); } diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 75509eb4c1..3c22f1d123 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -7,6 +7,7 @@ #include <string.h> #include <console/console.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> #include <device/pci_ops.h> #include <arch/ioapic.h> @@ -244,7 +245,7 @@ unsigned long southbridge_write_acpi_tables(const struct device *device, return acpi_write_hpet(device, current, rsdp); } -static void acpi_create_gnvs(struct global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* Clear out GNVS. */ memset(gnvs, 0, sizeof(*gnvs)); @@ -268,7 +269,7 @@ static void acpi_create_gnvs(struct global_nvs_t *gnvs) void southbridge_inject_dsdt(const struct device *device) { - struct global_nvs_t *gnvs; + struct global_nvs *gnvs; gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h index e5bc3f3ad4..09f60d7280 100644 --- a/src/soc/amd/picasso/include/soc/acpi.h +++ b/src/soc/amd/picasso/include/soc/acpi.h @@ -8,8 +8,6 @@ unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); -void southbridge_inject_dsdt(const struct device *device); - uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, acpi_rsdp_t *rsdp); diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h index 83f6afb289..214ab1d0bc 100644 --- a/src/soc/amd/picasso/include/soc/nvs.h +++ b/src/soc/amd/picasso/include/soc/nvs.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* - * NOTE: The layout of the global_nvs_t structure below must match the layout + * NOTE: The layout of the global_nvs structure below must match the layout * in soc/soc/amd/picasso/acpi/globalnvs.asl !!! * */ @@ -14,7 +14,7 @@ #include <vendorcode/google/chromeos/gnvs.h> #include <soc/southbridge.h> -typedef struct global_nvs_t { +struct __packed global_nvs { /* Miscellaneous */ uint8_t pcnt; /* 0x00 - Processor Count */ uint8_t ppcm; /* 0x01 - Max PPC State */ @@ -41,7 +41,8 @@ typedef struct global_nvs_t { /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; -} __packed global_nvs_t; -check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); +}; + +check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); #endif /* __SOC_PICASSO_NVS_H__ */ diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 45f66d6b5b..cb22195546 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -303,7 +303,7 @@ static int get_index_bit(uint32_t value, uint16_t limit) static void set_nvs_sws(void *unused) { struct soc_power_reg *sws; - struct global_nvs_t *gnvs; + struct global_nvs *gnvs; int index; sws = cbmem_find(CBMEM_ID_POWER_STATE); @@ -337,7 +337,7 @@ void southbridge_init(void *chip_info) static void set_sb_final_nvs(void) { - struct global_nvs_t *gnvs = acpi_get_gnvs(); + struct global_nvs *gnvs = acpi_get_gnvs(); if (gnvs == NULL) return; diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 19dee79a96..81a82c736a 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -7,6 +7,7 @@ #include <string.h> #include <console/console.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> #include <device/pci_ops.h> #include <arch/ioapic.h> @@ -219,7 +220,7 @@ unsigned long southbridge_write_acpi_tables(const struct device *device, return acpi_write_hpet(device, current, rsdp); } -static void acpi_create_gnvs(struct global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* Clear out GNVS. */ memset(gnvs, 0, sizeof(*gnvs)); @@ -243,7 +244,7 @@ static void acpi_create_gnvs(struct global_nvs_t *gnvs) void southbridge_inject_dsdt(const struct device *device) { - struct global_nvs_t *gnvs; + struct global_nvs *gnvs; gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); diff --git a/src/soc/amd/stoneyridge/include/soc/acpi.h b/src/soc/amd/stoneyridge/include/soc/acpi.h index c44e934225..9617b45eca 100644 --- a/src/soc/amd/stoneyridge/include/soc/acpi.h +++ b/src/soc/amd/stoneyridge/include/soc/acpi.h @@ -14,8 +14,6 @@ unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); -void southbridge_inject_dsdt(const struct device *device); - const char *soc_acpi_name(const struct device *dev); #endif /* __SOC_STONEYRIDGE_ACPI_H__ */ diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h index 2b949c9c3b..864cfffa1a 100644 --- a/src/soc/amd/stoneyridge/include/soc/nvs.h +++ b/src/soc/amd/stoneyridge/include/soc/nvs.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* - * NOTE: The layout of the global_nvs_t structure below must match the layout + * NOTE: The layout of the global_nvs structure below must match the layout * in soc/soc/amd/stoneyridge/acpi/globalnvs.asl !!! * */ @@ -14,7 +14,7 @@ #include <vendorcode/google/chromeos/gnvs.h> #include <soc/southbridge.h> -typedef struct global_nvs_t { +struct __packed global_nvs { /* Miscellaneous */ uint8_t pcnt; /* 0x00 - Processor Count */ uint8_t ppcm; /* 0x01 - Max PPC State */ @@ -46,7 +46,8 @@ typedef struct global_nvs_t { /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; -} __packed global_nvs_t; -check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); +}; + +check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); #endif /* __SOC_STONEYRIDGE_NVS_H__ */ diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index f21734902b..15219b42a2 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -537,7 +537,7 @@ static int get_index_bit(uint32_t value, uint16_t limit) static void set_nvs_sws(void *unused) { struct soc_power_reg *sws; - struct global_nvs_t *gnvs; + struct global_nvs *gnvs; int index; sws = cbmem_find(CBMEM_ID_POWER_STATE); @@ -576,7 +576,7 @@ static void set_sb_final_nvs(void) size_t fwsize; const struct device *sd, *sata; - struct global_nvs_t *gnvs = acpi_get_gnvs(); + struct global_nvs *gnvs = acpi_get_gnvs(); if (gnvs == NULL) return; diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 595e6a2920..1c7a04a703 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> #include <console/console.h> #include <device/mmio.h> @@ -70,7 +71,7 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries) return cstate_map; } -void acpi_create_gnvs(struct global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { struct soc_intel_apollolake_config *cfg; cfg = config_of_soc(); diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index f9af4f49d9..dd7dd1a4e0 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -320,7 +320,7 @@ static void soc_init(void *data) p2sb_unhide(); /* Allocate ACPI NVS in CBMEM */ - cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs_t)); + cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs)); if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) { printk(BIOS_INFO, "Skip setting RAPL per configuration\n"); diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index 4668e1a07f..45301c4aa4 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* - * NOTE: The layout of the global_nvs_t structure below must match the layout + * NOTE: The layout of the global_nvs structure below must match the layout * in soc/intel/apollolake/acpi/globalnvs.asl !!! * */ @@ -12,7 +12,7 @@ #include <commonlib/helpers.h> #include <vendorcode/google/chromeos/gnvs.h> -typedef struct global_nvs_t { +struct __packed global_nvs { /* Miscellaneous */ uint8_t pcnt; /* 0x00 - Processor Count */ uint8_t ppcm; /* 0x01 - Max PPC State */ @@ -38,7 +38,8 @@ typedef struct global_nvs_t { /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; -} __packed global_nvs_t; -check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); +}; + +check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); #endif /* _SOC_APOLLOLAKE_NVS_H_ */ diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 13acf86ada..9bcd78698b 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> #include <device/mmio.h> #include <arch/smp/mpspec.h> @@ -57,7 +58,7 @@ static acpi_cstate_t cstate_map[] = { } }; -void acpi_init_gnvs(global_nvs_t *gnvs) +void acpi_init_gnvs(struct global_nvs *gnvs) { /* Set unknown wake source */ gnvs->pm1i = -1; diff --git a/src/soc/intel/baytrail/include/soc/acpi.h b/src/soc/intel/baytrail/include/soc/acpi.h index fc8f8aba4c..98b8283fe4 100644 --- a/src/soc/intel/baytrail/include/soc/acpi.h +++ b/src/soc/intel/baytrail/include/soc/acpi.h @@ -7,6 +7,5 @@ #include <soc/nvs.h> unsigned long acpi_madt_irq_overrides(unsigned long current); -void acpi_init_gnvs(global_nvs_t *gnvs); #endif /* _BAYTRAIL_ACPI_H_ */ diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h index cc70f78b2a..cdffc75768 100644 --- a/src/soc/intel/baytrail/include/soc/nvs.h +++ b/src/soc/intel/baytrail/include/soc/nvs.h @@ -7,7 +7,7 @@ #include <vendorcode/google/chromeos/gnvs.h> #include <soc/device_nvs.h> -typedef struct global_nvs_t { +struct __packed global_nvs { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ u8 smif; /* 0x02 - SMI function call ("TRAP") */ @@ -53,12 +53,8 @@ typedef struct global_nvs_t { /* Baytrail LPSS (0x1000) */ device_nvs_t dev; -} __packed global_nvs_t; -check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); +}; -void acpi_create_gnvs(global_nvs_t *gnvs); - -/* Used in SMM to find the ACPI GNVS address */ -global_nvs_t *smm_get_gnvs(void); +check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); #endif /* _BAYTRAIL_NVS_H_ */ diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c index 78638de816..3a12a4b5a8 100644 --- a/src/soc/intel/baytrail/lpe.c +++ b/src/soc/intel/baytrail/lpe.c @@ -50,7 +50,7 @@ static void lpe_enable_acpi_mode(struct device *dev) LPE_PCICFGCTR1_ACPI_INT_EN), REG_SCRIPT_END }; - global_nvs_t *gnvs; + struct global_nvs *gnvs; /* Find ACPI NVS to update BARs */ gnvs = acpi_get_gnvs(); diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c index d5c3e4de31..cdf78b7314 100644 --- a/src/soc/intel/baytrail/lpss.c +++ b/src/soc/intel/baytrail/lpss.c @@ -28,7 +28,7 @@ static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, REG_SCRIPT_END }; struct resource *bar; - global_nvs_t *gnvs; + struct global_nvs *gnvs; /* Find ACPI NVS to update BARs */ gnvs = acpi_get_gnvs(); diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index d27a17dcd1..995fe20679 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -117,7 +117,7 @@ static void fill_in_pattrs(void) } /* Save bit index for first enabled event in PM1_STS for \_SB._SWS */ -static void s3_save_acpi_wake_source(global_nvs_t *gnvs) +static void s3_save_acpi_wake_source(struct global_nvs *gnvs) { struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); uint16_t pm1; @@ -144,14 +144,14 @@ static void s3_save_acpi_wake_source(global_nvs_t *gnvs) static void s3_resume_prepare(void) { - global_nvs_t *gnvs; + struct global_nvs *gnvs; - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs)); if (gnvs == NULL) return; if (!acpi_is_wakeup_s3()) - memset(gnvs, 0, sizeof(global_nvs_t)); + memset(gnvs, 0, sizeof(struct global_nvs)); else s3_save_acpi_wake_source(gnvs); } diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c index 455f243184..f178e83d28 100644 --- a/src/soc/intel/baytrail/scc.c +++ b/src/soc/intel/baytrail/scc.c @@ -81,7 +81,7 @@ void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) REG_SCRIPT_END }; struct resource *bar; - global_nvs_t *gnvs; + struct global_nvs *gnvs; /* Find ACPI NVS to update BARs */ gnvs = acpi_get_gnvs(); diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 91eb6f561d..2a56f84949 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -19,7 +19,7 @@ #include <soc/nvs.h> /* GNVS needs to be set by coreboot initiating a software SMI. */ -static global_nvs_t *gnvs; +static struct global_nvs *gnvs; static int smm_initialized; int southbridge_io_trap_handler(int smif) @@ -44,7 +44,7 @@ void southbridge_smi_set_eos(void) enable_smi(EOS); } -global_nvs_t *smm_get_gnvs(void) +struct global_nvs *smm_get_gnvs(void) { return gnvs; } @@ -330,7 +330,7 @@ static void southbridge_smi_apmc(void) state = smi_apmc_find_state_save(reg8); if (state) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((uint32_t)state->rbx); + gnvs = (struct global_nvs *)((uint32_t)state->rbx); smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 679c04d491..38f51ff521 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -5,6 +5,7 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <bootstate.h> #include <cbmem.h> #include <console/console.h> @@ -482,7 +483,7 @@ void southcluster_enable_dev(struct device *dev) static void southcluster_inject_dsdt(const struct device *device) { - global_nvs_t *gnvs; + struct global_nvs *gnvs; gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (!gnvs) { diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 1290d625ac..98d7980995 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> #include <device/mmio.h> #include <arch/smp/mpspec.h> @@ -61,7 +62,7 @@ static acpi_cstate_t cstate_map[] = { } }; -void acpi_init_gnvs(global_nvs_t *gnvs) +void acpi_init_gnvs(struct global_nvs *gnvs) { /* Set unknown wake source */ gnvs->pm1i = -1; @@ -493,7 +494,7 @@ unsigned long southcluster_write_acpi_tables(const struct device *device, unsign void southcluster_inject_dsdt(const struct device *device) { - global_nvs_t *gnvs; + struct global_nvs *gnvs; gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (!gnvs) { diff --git a/src/soc/intel/braswell/include/soc/acpi.h b/src/soc/intel/braswell/include/soc/acpi.h index 5bff07a0fb..cd54f2c066 100644 --- a/src/soc/intel/braswell/include/soc/acpi.h +++ b/src/soc/intel/braswell/include/soc/acpi.h @@ -8,7 +8,6 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt); unsigned long acpi_madt_irq_overrides(unsigned long current); -void acpi_init_gnvs(global_nvs_t *gnvs); void southcluster_inject_dsdt(const struct device *device); unsigned long southcluster_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h index 22ea10fe93..35ab47a1e7 100644 --- a/src/soc/intel/braswell/include/soc/nvs.h +++ b/src/soc/intel/braswell/include/soc/nvs.h @@ -7,7 +7,7 @@ #include <soc/device_nvs.h> #include <vendorcode/google/chromeos/gnvs.h> -typedef struct global_nvs_t { +struct __packed global_nvs { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ u8 smif; /* 0x02 - SMI function call ("TRAP") */ @@ -55,11 +55,8 @@ typedef struct global_nvs_t { /* LPSS (0x1000) */ device_nvs_t dev; -} __packed global_nvs_t; -check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); +}; -void acpi_create_gnvs(global_nvs_t *gnvs); -/* Used in SMM to find the ACPI GNVS address */ -global_nvs_t *smm_get_gnvs(void); +check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); #endif /* _SOC_NVS_H_ */ diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index f3391de443..0fb4ca9bad 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -53,7 +53,7 @@ static void lpe_enable_acpi_mode(struct device *dev) REG_SCRIPT_END }; - global_nvs_t *gnvs; + struct global_nvs *gnvs; /* Find ACPI NVS to update BARs */ gnvs = acpi_get_gnvs(); diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c index 82002487af..d9027f5584 100644 --- a/src/soc/intel/braswell/lpss.c +++ b/src/soc/intel/braswell/lpss.c @@ -27,7 +27,7 @@ static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index REG_SCRIPT_END }; struct resource *bar; - global_nvs_t *gnvs; + struct global_nvs *gnvs; /* Find ACPI NVS to update BARs */ gnvs = acpi_get_gnvs(); diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index 893a6b6ea2..eba15274dd 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -137,16 +137,16 @@ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) static void s3_resume_prepare(void) { - global_nvs_t *gnvs; + struct global_nvs *gnvs; - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs)); if (!acpi_is_wakeup_s3() && gnvs) - memset(gnvs, 0, sizeof(global_nvs_t)); + memset(gnvs, 0, sizeof(struct global_nvs)); } static void set_board_id(void) { - global_nvs_t *gnvs; + struct global_nvs *gnvs; gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (!gnvs) { diff --git a/src/soc/intel/braswell/scc.c b/src/soc/intel/braswell/scc.c index 0b6385fc24..6f23fda119 100644 --- a/src/soc/intel/braswell/scc.c +++ b/src/soc/intel/braswell/scc.c @@ -12,7 +12,7 @@ void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) { struct resource *bar; - global_nvs_t *gnvs; + struct global_nvs *gnvs; printk(BIOS_SPEW, "%s/%s (%s, 0x%08x, 0x%08x)\n", __FILE__, __func__, dev_name(dev), iosf_reg, nvs_index); diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index 614f56dfdd..28765d0780 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -19,7 +19,7 @@ #include <smmstore.h> /* GNVS needs to be set by coreboot initiating a software SMI. */ -static global_nvs_t *gnvs; +static struct global_nvs *gnvs; static int smm_initialized; int southbridge_io_trap_handler(int smif) @@ -45,7 +45,7 @@ void southbridge_smi_set_eos(void) enable_smi(EOS); } -global_nvs_t *smm_get_gnvs(void) +struct global_nvs *smm_get_gnvs(void) { return gnvs; } @@ -307,7 +307,7 @@ static void southbridge_smi_apmc(void) state = smi_apmc_find_state_save(reg8); if (state) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((uint32_t)state->rbx); + gnvs = (struct global_nvs *)((uint32_t)state->rbx); smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 43ff8eb4ad..306d72f5f1 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> #include <arch/smp/mpspec.h> #include <cbmem.h> @@ -148,7 +149,7 @@ static int get_cores_per_package(void) return cores; } -void acpi_init_gnvs(global_nvs_t *gnvs) +void acpi_init_gnvs(struct global_nvs *gnvs) { /* Set unknown wake source */ gnvs->pm1i = -1; diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c index 897f9c4ee3..15858e1024 100644 --- a/src/soc/intel/broadwell/adsp.c +++ b/src/soc/intel/broadwell/adsp.c @@ -80,7 +80,7 @@ static void adsp_init(struct device *dev) if (config->sio_acpi_mode) { /* Configure for ACPI mode */ - global_nvs_t *gnvs; + struct global_nvs *gnvs; printk(BIOS_INFO, "ADSP: Enable ACPI Mode IRQ3\n"); diff --git a/src/soc/intel/broadwell/include/soc/acpi.h b/src/soc/intel/broadwell/include/soc/acpi.h index 46cc42a8e8..0bf63a495e 100644 --- a/src/soc/intel/broadwell/include/soc/acpi.h +++ b/src/soc/intel/broadwell/include/soc/acpi.h @@ -13,7 +13,6 @@ #define PSS_LATENCY_BUSMASTER 10 unsigned long acpi_madt_irq_overrides(unsigned long current); -void acpi_init_gnvs(global_nvs_t *gnvs); unsigned long northbridge_write_acpi_tables(const struct device *dev, unsigned long current, struct acpi_rsdp *rsdp); #endif diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h index 8772a02983..afeed6f53e 100644 --- a/src/soc/intel/broadwell/include/soc/nvs.h +++ b/src/soc/intel/broadwell/include/soc/nvs.h @@ -7,7 +7,7 @@ #include <soc/device_nvs.h> #include <vendorcode/google/chromeos/gnvs.h> -typedef struct global_nvs_t { +struct __packed global_nvs { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ u8 smif; /* 0x02 - SMI function call ("TRAP") */ @@ -45,12 +45,8 @@ typedef struct global_nvs_t { /* Device specific (0x1000) */ device_nvs_t dev; -} __packed global_nvs_t; -check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); +}; -void acpi_create_gnvs(global_nvs_t *gnvs); - -/* Used in SMM to find the ACPI GNVS address */ -global_nvs_t *smm_get_gnvs(void); +check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); #endif diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 1e96286990..58cd35d1f6 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -11,6 +11,7 @@ #include <device/pci_ops.h> #include <arch/ioapic.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <cpu/x86/smm.h> #include <cbmem.h> #include <reg_script.h> @@ -553,7 +554,7 @@ static void pch_lpc_add_io_resources(struct device *dev) static void pch_lpc_read_resources(struct device *dev) { - global_nvs_t *gnvs; + struct global_nvs *gnvs; /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); @@ -565,14 +566,14 @@ static void pch_lpc_read_resources(struct device *dev) pch_lpc_add_io_resources(dev); /* Allocate ACPI NVS in CBMEM */ - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs)); if (!acpi_is_wakeup_s3() && gnvs) - memset(gnvs, 0, sizeof(global_nvs_t)); + memset(gnvs, 0, sizeof(struct global_nvs)); } static void southcluster_inject_dsdt(const struct device *device) { - global_nvs_t *gnvs; + struct global_nvs *gnvs; gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (!gnvs) { diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c index 39550b778e..c414d62192 100644 --- a/src/soc/intel/broadwell/ramstage.c +++ b/src/soc/intel/broadwell/ramstage.c @@ -32,14 +32,14 @@ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) static void s3_resume_prepare(void) { - global_nvs_t *gnvs; + struct global_nvs *gnvs; - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs)); if (gnvs == NULL) return; if (!acpi_is_wakeup_s3()) - memset(gnvs, 0, sizeof(global_nvs_t)); + memset(gnvs, 0, sizeof(struct global_nvs)); } void broadwell_init_pre_device(void *chip_info) diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c index 4da3979ed5..dbe194a223 100644 --- a/src/soc/intel/broadwell/serialio.c +++ b/src/soc/intel/broadwell/serialio.c @@ -233,7 +233,7 @@ static void serialio_init(struct device *dev) } if (config->sio_acpi_mode) { - global_nvs_t *gnvs; + struct global_nvs *gnvs; /* Find ACPI NVS to update BARs */ gnvs = acpi_get_gnvs(); diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index 85d6ae02b5..c7cefdc576 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -29,8 +29,8 @@ static u8 smm_initialized = 0; * GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located * by coreboot. */ -static global_nvs_t *gnvs; -global_nvs_t *smm_get_gnvs(void) +static struct global_nvs *gnvs; +struct global_nvs *smm_get_gnvs(void) { return gnvs; } @@ -350,7 +350,7 @@ static void southbridge_smi_apmc(void) state = smi_apmc_find_state_save(reg8); if (state) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((u32)state->rbx); + gnvs = (struct global_nvs *)((u32)state->rbx); smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index c041eb003e..1f3fbeced2 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> #include <arch/smp/mpspec.h> #include <cbmem.h> @@ -182,7 +183,7 @@ uint32_t soc_read_sci_irq_select(void) return read32((void *)pmc_bar + IRQ_REG); } -void acpi_create_gnvs(struct global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { const struct soc_intel_cannonlake_config *config; config = config_of_soc(); diff --git a/src/soc/intel/common/acpi_wake_source.c b/src/soc/intel/common/acpi_wake_source.c index 1342c80ebd..f30ef9f0db 100644 --- a/src/soc/intel/common/acpi_wake_source.c +++ b/src/soc/intel/common/acpi_wake_source.c @@ -16,7 +16,7 @@ __weak int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) /* Save wake source data for ACPI _SWS methods in NVS */ static void acpi_save_wake_source(void *unused) { - global_nvs_t *gnvs = acpi_get_gnvs(); + struct global_nvs *gnvs = acpi_get_gnvs(); uint32_t pm1, *gpe0; int gpe_reg, gpe_reg_count; int reg_size = sizeof(uint32_t) * 8; diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 3265131f93..5e4c6e8e4c 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -222,13 +222,13 @@ static int acpi_fill_wake(uint32_t *pm1, uint32_t **gpe0) } #endif -__weak void acpi_create_gnvs(struct global_nvs_t *gnvs) +__weak void acpi_create_gnvs(struct global_nvs *gnvs) { } void southbridge_inject_dsdt(const struct device *device) { - struct global_nvs_t *gnvs; + struct global_nvs *gnvs; gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (!gnvs) { @@ -457,7 +457,7 @@ void generate_cpu_entries(const struct device *device) /* Save wake source data for ACPI _SWS methods in NVS */ static void acpi_save_wake_source(void *unused) { - global_nvs_t *gnvs = acpi_get_gnvs(); + struct global_nvs *gnvs = acpi_get_gnvs(); uint32_t pm1, *gpe0; int gpe_reg, gpe_reg_count; int reg_size = sizeof(uint32_t) * 8; diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index 19dd68af6c..21664c8716 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -12,7 +12,7 @@ struct chipset_power_state; /* Forward declare the global nvs structure here */ -struct global_nvs_t; +struct global_nvs; /* Return ACPI name for this device */ const char *soc_acpi_name(const struct device *dev); @@ -32,19 +32,6 @@ unsigned long southbridge_write_acpi_tables(const struct device *device, struct acpi_rsdp *rsdp); /* - * Creates acpi gnvs and adds it to the DSDT table. - * GNVS creation is chipset specific and is done in soc specific acpi.c file. - */ -void southbridge_inject_dsdt(const struct device *device); - -/* - * This function populates the gnvs structure in acpi table. - * Defined as weak in common acpi as gnvs structure definition is - * chipset specific. - */ -void acpi_create_gnvs(struct global_nvs_t *gnvs); - -/* * get_cstate_map returns a table of processor specific acpi_cstate_t entries * and number of entries in the table */ diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h index e1040eac3c..cc240c5760 100644 --- a/src/soc/intel/common/block/include/intelblocks/nvs.h +++ b/src/soc/intel/common/block/include/intelblocks/nvs.h @@ -6,7 +6,7 @@ #include <commonlib/helpers.h> #include <vendorcode/google/chromeos/gnvs.h> -typedef struct global_nvs_t { +struct __packed global_nvs { /* Miscellaneous */ u16 osys; /* 0x00 - 0x01 Operating System */ u8 smif; /* 0x02 - SMI function call ("TRAP") */ @@ -31,7 +31,8 @@ typedef struct global_nvs_t { /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; -} __packed global_nvs_t; -check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); +}; + +check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); #endif diff --git a/src/soc/intel/common/block/include/intelblocks/sgx.h b/src/soc/intel/common/block/include/intelblocks/sgx.h index e6c99057c2..56e4a167b5 100644 --- a/src/soc/intel/common/block/include/intelblocks/sgx.h +++ b/src/soc/intel/common/block/include/intelblocks/sgx.h @@ -18,6 +18,6 @@ void prmrr_core_configure(void); void sgx_configure(void *unused); /* Fill GNVS data with SGX status, EPC base and length */ -void sgx_fill_gnvs(global_nvs_t *gnvs); +void sgx_fill_gnvs(struct global_nvs *gnvs); #endif /* SOC_INTEL_COMMON_BLOCK_SGX_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/smihandler.h b/src/soc/intel/common/block/include/intelblocks/smihandler.h index 428a9f35b1..7cea1dd1ab 100644 --- a/src/soc/intel/common/block/include/intelblocks/smihandler.h +++ b/src/soc/intel/common/block/include/intelblocks/smihandler.h @@ -7,7 +7,7 @@ #include <stdint.h> struct gpi_status; -struct global_nvs_t; +struct global_nvs; /* * The register value is used with get_reg and set_reg @@ -127,11 +127,6 @@ void smihandler_southbridge_gpi( void smihandler_southbridge_espi( const struct smm_save_state_ops *save_state_ops); -/* - * Returns gnvs pointer within SMM context - */ -struct global_nvs_t *smm_get_gnvs(void); - /* SoC overrides. */ /* Specific SOC SMI handler during ramstage finalize phase */ diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h index ae7211697e..cf5613853e 100644 --- a/src/soc/intel/common/block/include/intelblocks/systemagent.h +++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h @@ -71,7 +71,7 @@ uintptr_t sa_get_tseg_base(void); /* API to get TSEG size */ size_t sa_get_tseg_size(void); /* Fill MMIO resource above 4GB into GNVS */ -void sa_fill_gnvs(global_nvs_t *gnvs); +void sa_fill_gnvs(struct global_nvs *gnvs); /* * SoC overrides * diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 9fe48d1f87..ea85911732 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpi_gnvs.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c index 56648c81ea..8679f1f011 100644 --- a/src/soc/intel/common/block/sgx/sgx.c +++ b/src/soc/intel/common/block/sgx/sgx.c @@ -235,7 +235,7 @@ void sgx_configure(void *unused) activate_sgx(); } -void sgx_fill_gnvs(global_nvs_t *gnvs) +void sgx_fill_gnvs(struct global_nvs *gnvs) { struct cpuid_result cpuid_regs; diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index ab5e9c29da..73dfda5741 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -27,7 +27,7 @@ #include <stdint.h> /* GNVS needs to be set by coreboot initiating a software SMI. */ -static struct global_nvs_t *gnvs; +static struct global_nvs *gnvs; /* SoC overrides. */ @@ -125,7 +125,7 @@ void southbridge_smi_set_eos(void) pmc_enable_smi(EOS); } -struct global_nvs_t *smm_get_gnvs(void) +struct global_nvs *smm_get_gnvs(void) { return gnvs; } @@ -380,7 +380,7 @@ void smihandler_southbridge_apmc( if (state) { /* EBX in the state save contains the GNVS pointer */ uint32_t reg_ebx = save_state_ops->get_reg(state, RBX); - gnvs = (struct global_nvs_t *)(uintptr_t)reg_ebx; + gnvs = (struct global_nvs *)(uintptr_t)reg_ebx; smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } diff --git a/src/soc/intel/common/block/smm/smitraphandler.c b/src/soc/intel/common/block/smm/smitraphandler.c index 1e9f4d9c57..1d6fb816bb 100644 --- a/src/soc/intel/common/block/smm/smitraphandler.c +++ b/src/soc/intel/common/block/smm/smitraphandler.c @@ -24,7 +24,7 @@ /* Inherited from cpu/x86/smm.h resulting in a different signature */ int southbridge_io_trap_handler(int smif) { - global_nvs_t *gnvs = smm_get_gnvs(); + struct global_nvs *gnvs = smm_get_gnvs(); switch (smif) { case 0x32: printk(BIOS_DEBUG, "OS Init\n"); @@ -61,7 +61,7 @@ void smihandler_southbridge_monitor( u32 data, mask = 0; u8 trap_sts; int i; - global_nvs_t *gnvs = smm_get_gnvs(); + struct global_nvs *gnvs = smm_get_gnvs(); /* TRSR - Trap Status Register */ trap_sts = pcr_read8(PID_PSTH, PCR_PSTH_TRPST); diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index d25e1aa46c..e6bbfc7d63 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -103,7 +103,7 @@ static void sa_read_map_entry(struct device *dev, } /* Fill MMIO resource above 4GB into GNVS */ -void sa_fill_gnvs(global_nvs_t *gnvs) +void sa_fill_gnvs(struct global_nvs *gnvs) { struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 0c641f3746..fac05775fa 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -167,7 +167,7 @@ static void uart_read_resources(struct device *dev) */ static bool pch_uart_init_debug_controller_on_resume(void) { - global_nvs_t *gnvs = acpi_get_gnvs(); + struct global_nvs *gnvs = acpi_get_gnvs(); if (gnvs) return !!gnvs->uior; diff --git a/src/soc/intel/common/nhlt.c b/src/soc/intel/common/nhlt.c index 099be5d8bd..39baf016c2 100644 --- a/src/soc/intel/common/nhlt.c +++ b/src/soc/intel/common/nhlt.c @@ -13,7 +13,7 @@ uintptr_t nhlt_soc_serialize_oem_overrides(struct nhlt *nhlt, uintptr_t acpi_addr, const char *oem_id, const char *oem_table_id, uint32_t oem_revision) { - global_nvs_t *gnvs; + struct global_nvs *gnvs; gnvs = acpi_get_gnvs(); diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 3f416b6cd9..92a9c2a771 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> #include <arch/smp/mpspec.h> #include <cpu/x86/smm.h> @@ -57,7 +58,7 @@ static acpi_cstate_t cstate_map[] = { } }; -void acpi_init_gnvs(global_nvs_t *gnvs) +void acpi_init_gnvs(struct global_nvs *gnvs) { /* CPU core count */ gnvs->pcnt = dev_count_cpu(); @@ -280,7 +281,7 @@ unsigned long southcluster_write_acpi_tables(const struct device *device, void southcluster_inject_dsdt(const struct device *device) { - global_nvs_t *gnvs; + struct global_nvs *gnvs; gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (!gnvs) { diff --git a/src/soc/intel/denverton_ns/include/soc/acpi.h b/src/soc/intel/denverton_ns/include/soc/acpi.h index 00700a6aab..9bc5ed0924 100644 --- a/src/soc/intel/denverton_ns/include/soc/acpi.h +++ b/src/soc/intel/denverton_ns/include/soc/acpi.h @@ -8,7 +8,6 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt); unsigned long acpi_madt_irq_overrides(unsigned long current); -void acpi_init_gnvs(global_nvs_t *gnvs); unsigned long southcluster_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); diff --git a/src/soc/intel/denverton_ns/include/soc/nvs.h b/src/soc/intel/denverton_ns/include/soc/nvs.h index 0195643a51..4aaabc9538 100644 --- a/src/soc/intel/denverton_ns/include/soc/nvs.h +++ b/src/soc/intel/denverton_ns/include/soc/nvs.h @@ -3,7 +3,7 @@ #ifndef _DENVERTON_NS_NVS_H_ #define _DENVERTON_NS_NVS_H_ -typedef struct global_nvs_t { +struct __packed global_nvs { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ u8 smif; /* 0x02 - SMI function call ("TRAP") */ @@ -47,9 +47,6 @@ typedef struct global_nvs_t { u32 tsegl; /* 0x58 - TSEG Length/Size */ u8 rsvd3[164]; -} __packed global_nvs_t; - -/* Used in SMM to find the ACPI GNVS address */ -global_nvs_t *smm_get_gnvs(void); +}; #endif /* _DENVERTON_NS_NVS_H_ */ diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index b81eb1157f..aa87630906 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -17,7 +17,7 @@ #include <soc/nvs.h> /* GNVS needs to be set by coreboot initiating a software SMI. */ -static global_nvs_t *gnvs; +static struct global_nvs *gnvs; static int smm_initialized; int southbridge_io_trap_handler(int smif) @@ -39,7 +39,7 @@ int southbridge_io_trap_handler(int smif) void southbridge_smi_set_eos(void) { enable_smi(EOS); } -global_nvs_t *smm_get_gnvs(void) { return gnvs; } +struct global_nvs *smm_get_gnvs(void) { return gnvs; } static void busmaster_disable_on_bus(int bus) { @@ -241,7 +241,7 @@ static void southbridge_smi_apmc(void) state = smi_apmc_find_state_save(reg8); if (state) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((uint32_t)state->rbx); + gnvs = (struct global_nvs *)((uint32_t)state->rbx); smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 796e770c89..ece28ccc35 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> #include <device/mmio.h> #include <arch/smp/mpspec.h> @@ -178,7 +179,7 @@ uint32_t soc_read_sci_irq_select(void) return read32((void *)pmc_bar + IRQ_REG); } -void acpi_create_gnvs(struct global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { config_t *config = config_of_soc(); diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index 88ec5fedd6..9d5080b681 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> #include <device/mmio.h> #include <arch/smp/mpspec.h> @@ -272,7 +273,7 @@ unsigned long sa_write_acpi_tables(const struct device *dev, unsigned long curre return current; } -void acpi_create_gnvs(struct global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { config_t *config = config_of_soc(); diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 6fde1e2df7..6da43e9610 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> #include <arch/cpu.h> #include <arch/ioapic.h> @@ -155,7 +156,7 @@ static int get_cores_per_package(void) return cores; } -static void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { const struct soc_intel_skylake_config *config = config_of_soc(); @@ -643,7 +644,7 @@ unsigned long southbridge_write_acpi_tables(const struct device *device, void southbridge_inject_dsdt(const struct device *device) { - global_nvs_t *gnvs; + struct global_nvs *gnvs; gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (!gnvs) { diff --git a/src/soc/intel/skylake/include/soc/acpi.h b/src/soc/intel/skylake/include/soc/acpi.h index 3422ece7de..bf81afb44e 100644 --- a/src/soc/intel/skylake/include/soc/acpi.h +++ b/src/soc/intel/skylake/include/soc/acpi.h @@ -13,7 +13,6 @@ #define PSS_LATENCY_BUSMASTER 10 unsigned long acpi_madt_irq_overrides(unsigned long current); -void southbridge_inject_dsdt(const struct device *device); unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); unsigned long northbridge_write_acpi_tables(const struct device *, diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index 4973597947..87f16fb5f9 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -6,7 +6,7 @@ #include <commonlib/helpers.h> #include <vendorcode/google/chromeos/gnvs.h> -typedef struct global_nvs_t { +struct __packed global_nvs { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ u8 smif; /* 0x02 - SMI function call ("TRAP") */ @@ -51,7 +51,8 @@ typedef struct global_nvs_t { /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; -} __packed global_nvs_t; -check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); +}; + +check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); #endif diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index 0991134ed9..4b31c6d48a 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> #include <device/mmio.h> #include <arch/smp/mpspec.h> @@ -272,7 +273,7 @@ unsigned long sa_write_acpi_tables(const struct device *dev, unsigned long curre return current; } -void acpi_create_gnvs(struct global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { config_t *config = config_of_soc(); diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index e52d75d119..c554977e22 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> @@ -108,7 +109,7 @@ static void uncore_inject_dsdt(void) void southbridge_inject_dsdt(const struct device *device) { - global_nvs_t *gnvs; + struct global_nvs *gnvs; gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (!gnvs) { @@ -133,7 +134,7 @@ void southbridge_inject_dsdt(const struct device *device) uncore_inject_dsdt(); } -void acpi_create_gnvs(struct global_nvs_t *gnvs) +void acpi_create_gnvs(struct global_nvs *gnvs) { /* CPU core count */ gnvs->pcnt = dev_count_cpu(); diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/nvs.h b/src/soc/intel/xeon_sp/cpx/include/soc/nvs.h index 08ad0f7444..becdd76570 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/nvs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/nvs.h @@ -8,10 +8,10 @@ /* TODO - this requires xeon sp, server board support */ /* NOTE: We do not use intelblocks/nvs.h since it includes mostly client specific attributes */ -typedef struct global_nvs_t { +struct __packed global_nvs { uint8_t pcnt; /* 0x00 - Processor Count */ uint32_t cbmc; /* 0x01 - coreboot memconsole */ uint8_t rsvd3[251]; -} __packed global_nvs_t; +}; #endif /* _SOC_NVS_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c index 606bfedd1d..903fc732cd 100644 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <assert.h> +#include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> #include <arch/smp/mpspec.h> #include <intelblocks/acpi.h> @@ -47,7 +48,7 @@ static int acpi_sci_irq(void) return sci_irq; } -void acpi_init_gnvs(global_nvs_t *gnvs) +void acpi_init_gnvs(struct global_nvs *gnvs) { /* CPU core count */ gnvs->pcnt = dev_count_cpu(); @@ -956,7 +957,7 @@ void uncore_inject_dsdt(void) void southbridge_inject_dsdt(const struct device *device) { - global_nvs_t *gnvs; + struct global_nvs *gnvs; gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (!gnvs) { diff --git a/src/soc/intel/xeon_sp/skx/include/soc/acpi.h b/src/soc/intel/xeon_sp/skx/include/soc/acpi.h index c1d61c9025..0e00c2b4b6 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/acpi.h @@ -14,7 +14,6 @@ typedef struct { void acpi_create_serialio_ssdt(acpi_header_t *ssdt); unsigned long acpi_madt_irq_overrides(unsigned long current); -void acpi_init_gnvs(global_nvs_t *gnvs); unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); void uncore_inject_dsdt(void); diff --git a/src/soc/intel/xeon_sp/skx/include/soc/nvs.h b/src/soc/intel/xeon_sp/skx/include/soc/nvs.h index 08ad0f7444..becdd76570 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/nvs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/nvs.h @@ -8,10 +8,10 @@ /* TODO - this requires xeon sp, server board support */ /* NOTE: We do not use intelblocks/nvs.h since it includes mostly client specific attributes */ -typedef struct global_nvs_t { +struct __packed global_nvs { uint8_t pcnt; /* 0x00 - Processor Count */ uint32_t cbmc; /* 0x01 - coreboot memconsole */ uint8_t rsvd3[251]; -} __packed global_nvs_t; +}; #endif /* _SOC_NVS_H_ */ diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index e41bca260e..80d3a46380 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -12,6 +12,7 @@ #include <arch/io.h> #include <arch/ioapic.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> #include <cpu/x86/smm.h> #include <cbmem.h> @@ -647,9 +648,9 @@ static void pch_lpc_enable(struct device *dev) pch_enable(dev); } -static void southbridge_inject_dsdt(const struct device *dev) +void southbridge_inject_dsdt(const struct device *dev) { - global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); + struct global_nvs *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); if (gnvs) { memset(gnvs, 0, sizeof(*gnvs)); diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index 075eae0921..ae3304ee8e 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -4,7 +4,7 @@ #include <stdint.h> #include "vendorcode/google/chromeos/gnvs.h" -typedef struct global_nvs_t { +struct __packed global_nvs { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ u8 smif; /* 0x02 - SMI function call ("TRAP") */ @@ -102,9 +102,6 @@ typedef struct global_nvs_t { /* ChromeOS specific (starts at 0x100)*/ chromeos_acpi_t chromeos; -} __packed global_nvs_t; -check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); +}; -/* Used in SMM to find the ACPI GNVS address */ -global_nvs_t *smm_get_gnvs(void); -void acpi_create_gnvs(global_nvs_t *gnvs); +check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 83799bee1d..b257fb69fb 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -17,8 +17,8 @@ #include "pch.h" #include "nvs.h" -static global_nvs_t *gnvs; -global_nvs_t *smm_get_gnvs(void) +static struct global_nvs *gnvs; +struct global_nvs *smm_get_gnvs(void) { return gnvs; } @@ -196,7 +196,7 @@ void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) smi_apmc_find_state_save(apm_cnt); if (state) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((u32)state->rbx); + gnvs = (struct global_nvs *)((u32)state->rbx); *smm_done = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } diff --git a/src/southbridge/intel/i82801dx/nvs.h b/src/southbridge/intel/i82801dx/nvs.h index 9bd16786a3..3cd0afb1a9 100644 --- a/src/southbridge/intel/i82801dx/nvs.h +++ b/src/southbridge/intel/i82801dx/nvs.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -typedef struct { +struct __packed global_nvs { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ u8 smif; /* 0x02 - SMI function call ("TRAP") */ @@ -95,4 +95,4 @@ typedef struct { u8 dock; /* 0xf0 - Docking Status */ u8 bten; u8 rsvd13[14]; -} __packed global_nvs_t; +}; diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index b526a1aed0..7cd5c7056c 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -33,7 +33,7 @@ u8 mbi_initialized = 0; /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located * by coreboot. */ -global_nvs_t *gnvs = (global_nvs_t *)0x0; +struct global_nvs *gnvs = (struct global_nvs *)0x0; void *tcg = (void *)0x0; void *smi1 = (void *)0x0; diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 3b204d44c2..9b32f6cfd9 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -12,6 +12,7 @@ #include <device/pci_ops.h> #include <arch/ioapic.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <cpu/x86/smm.h> #include <acpi/acpigen.h> #include <arch/smp/mpspec.h> @@ -490,9 +491,9 @@ static void lpc_final(struct device *dev) outb(POST_OS_BOOT, 0x80); } -static void southbridge_inject_dsdt(const struct device *dev) +void southbridge_inject_dsdt(const struct device *dev) { - global_nvs_t *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); + struct global_nvs *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); if (gnvs) { memset(gnvs, 0, sizeof(*gnvs)); diff --git a/src/southbridge/intel/i82801gx/nvs.h b/src/southbridge/intel/i82801gx/nvs.h index 3f44330e5d..d2efc5c8b1 100644 --- a/src/southbridge/intel/i82801gx/nvs.h +++ b/src/southbridge/intel/i82801gx/nvs.h @@ -2,9 +2,10 @@ #ifndef SOUTHBRIDGE_INTEL_I82801GX_NVS_H #define SOUTHBRIDGE_INTEL_I82801GX_NVS_H + #include <stdint.h> -typedef struct { +struct __packed global_nvs { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ u8 smif; /* 0x02 - SMI function call ("TRAP") */ @@ -96,8 +97,6 @@ typedef struct { u8 dock; /* 0xf0 - Docking Status */ u8 bten; u8 rsvd13[14]; -} __packed global_nvs_t; - -void acpi_create_gnvs(global_nvs_t *gnvs); +}; #endif /* SOUTHBRIDGE_INTEL_I82801GX_NVS_H */ diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index ad0d358abd..1757872f2b 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -22,11 +22,11 @@ u16 pmbase = DEFAULT_PMBASE; u8 smm_initialized = 0; /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located by coreboot. */ -global_nvs_t *gnvs = (global_nvs_t *)0x0; +struct global_nvs *gnvs = (struct global_nvs *)0x0; void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { - gnvs = *(global_nvs_t **)0x500; + gnvs = *(struct global_nvs **)0x500; *smm_done = 1; } diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 7ddd883324..883c96428f 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -12,6 +12,7 @@ #include <device/pci_ops.h> #include <arch/ioapic.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <cpu/x86/smm.h> #include <acpi/acpigen.h> #include <cbmem.h> @@ -456,9 +457,9 @@ static void i82801ix_lpc_read_resources(struct device *dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void southbridge_inject_dsdt(const struct device *dev) +void southbridge_inject_dsdt(const struct device *dev) { - global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); + struct global_nvs *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); if (gnvs) { memset(gnvs, 0, sizeof(*gnvs)); diff --git a/src/southbridge/intel/i82801ix/nvs.h b/src/southbridge/intel/i82801ix/nvs.h index 3cd4c58d7c..e0e6bbd68d 100644 --- a/src/southbridge/intel/i82801ix/nvs.h +++ b/src/southbridge/intel/i82801ix/nvs.h @@ -2,9 +2,10 @@ #ifndef SOUTHBRIDGE_INTEL_I82801IX_NVS_H #define SOUTHBRIDGE_INTEL_I82801IX_NVS_H + #include <stdint.h> -typedef struct { +struct __packed global_nvs { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ u8 smif; /* 0x02 - SMI function call ("TRAP") */ @@ -96,8 +97,6 @@ typedef struct { u8 dock; /* 0xf0 - Docking Status */ u8 bten; u8 rsvd13[14]; -} __packed global_nvs_t; - -void acpi_create_gnvs(global_nvs_t *gnvs); +}; #endif /* SOUTHBRIDGE_INTEL_I82801IX_NVS_H */ diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index df3026e28f..070b7a60b8 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -12,7 +12,7 @@ /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located * by coreboot. */ -global_nvs_t *gnvs = (global_nvs_t *)0x0; +struct global_nvs *gnvs = (struct global_nvs *)0x0; void *tcg = (void *)0x0; void *smi1 = (void *)0x0; @@ -35,7 +35,7 @@ int southbridge_io_trap_handler(int smif) void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { - gnvs = *(global_nvs_t **)0x500; + gnvs = *(struct global_nvs **)0x500; tcg = *(void **)0x504; smi1 = *(void **)0x508; *smm_done = 1; diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index c36009ed0a..2533d8cc72 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -12,6 +12,7 @@ #include <device/pci_ops.h> #include <arch/ioapic.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <cpu/x86/smm.h> #include <acpi/acpigen.h> #include <arch/smp/mpspec.h> @@ -497,9 +498,9 @@ static void i82801jx_lpc_read_resources(struct device *dev) } } -static void southbridge_inject_dsdt(const struct device *dev) +void southbridge_inject_dsdt(const struct device *dev) { - global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); + struct global_nvs *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); if (gnvs) { memset(gnvs, 0, sizeof(*gnvs)); diff --git a/src/southbridge/intel/i82801jx/nvs.h b/src/southbridge/intel/i82801jx/nvs.h index c4879189ee..48a7d87fe1 100644 --- a/src/southbridge/intel/i82801jx/nvs.h +++ b/src/southbridge/intel/i82801jx/nvs.h @@ -4,7 +4,7 @@ #define SOUTHBRIDGE_INTEL_I82801JX_NVS_H #include <stdint.h> -typedef struct { +struct __packed global_nvs { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ u8 smif; /* 0x02 - SMI function call ("TRAP") */ @@ -96,8 +96,6 @@ typedef struct { u8 dock; /* 0xf0 - Docking Status */ u8 bten; u8 rsvd13[14]; -} __packed global_nvs_t; - -void acpi_create_gnvs(global_nvs_t *gnvs); +}; #endif /* SOUTHBRIDGE_INTEL_I82801JX_NVS_H */ diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c index 00b3ffaf72..af242aaf19 100644 --- a/src/southbridge/intel/i82801jx/smihandler.c +++ b/src/southbridge/intel/i82801jx/smihandler.c @@ -18,7 +18,7 @@ u8 smm_initialized = 0; /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located * by coreboot. */ -global_nvs_t *gnvs = (global_nvs_t *)0x0; +struct global_nvs *gnvs = (struct global_nvs *)0x0; void *tcg = (void *)0x0; void *smi1 = (void *)0x0; @@ -41,7 +41,7 @@ int southbridge_io_trap_handler(int smif) void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { - gnvs = *(global_nvs_t **)0x500; + gnvs = *(struct global_nvs **)0x500; tcg = *(void **)0x504; smi1 = *(void **)0x508; *smm_done = 1; diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 36d46f209a..2c2904627e 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -13,6 +13,7 @@ #include <device/pci_ops.h> #include <arch/ioapic.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <elog.h> #include <acpi/acpigen.h> #include <cbmem.h> @@ -552,9 +553,9 @@ static void pch_lpc_enable(struct device *dev) pch_enable(dev); } -static void southbridge_inject_dsdt(const struct device *dev) +void southbridge_inject_dsdt(const struct device *dev) { - global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); + struct global_nvs *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); if (gnvs) { memset(gnvs, 0, sizeof(*gnvs)); diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h index 6b82de33b2..834b3af8a8 100644 --- a/src/southbridge/intel/ibexpeak/nvs.h +++ b/src/southbridge/intel/ibexpeak/nvs.h @@ -3,7 +3,7 @@ #include <commonlib/helpers.h> #include "vendorcode/google/chromeos/gnvs.h" -typedef struct global_nvs_t { +struct __packed global_nvs { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ u8 smif; /* 0x02 - SMI function call ("TRAP") */ @@ -99,10 +99,6 @@ typedef struct global_nvs_t { /* ChromeOS specific (starts at 0x100)*/ chromeos_acpi_t chromeos; -} __packed global_nvs_t; -check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); +}; -/* Used in SMM to find the ACPI GNVS address */ -global_nvs_t *smm_get_gnvs(void); - -void acpi_create_gnvs(global_nvs_t *gnvs); +check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index a881f33dab..2679351436 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -26,8 +26,8 @@ /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located * by coreboot. */ -static global_nvs_t *gnvs; -global_nvs_t *smm_get_gnvs(void) +static struct global_nvs *gnvs; +struct global_nvs *smm_get_gnvs(void) { return gnvs; } @@ -160,7 +160,7 @@ void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) smi_apmc_find_state_save(apm_cnt); if (state) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((u32)state->rbx); + gnvs = (struct global_nvs *)((u32)state->rbx); *smm_done = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c index c4ea418ade..cfdcee6896 100644 --- a/src/southbridge/intel/lynxpoint/acpi.c +++ b/src/southbridge/intel/lynxpoint/acpi.c @@ -41,7 +41,7 @@ void acpi_create_intel_hpet(acpi_hpet_t * hpet) acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); } -static void acpi_create_serialio_ssdt_entry(int id, global_nvs_t *gnvs) +static void acpi_create_serialio_ssdt_entry(int id, struct global_nvs *gnvs) { char sio_name[5] = {}; snprintf(sio_name, sizeof(sio_name), "S%1uEN", id); @@ -51,7 +51,7 @@ static void acpi_create_serialio_ssdt_entry(int id, global_nvs_t *gnvs) void acpi_create_serialio_ssdt(acpi_header_t *ssdt) { unsigned long current = (unsigned long)ssdt + sizeof(acpi_header_t); - global_nvs_t *gnvs = acpi_get_gnvs(); + struct global_nvs *gnvs = acpi_get_gnvs(); int id; if (!gnvs) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 78536f6c10..f486434045 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -11,6 +11,7 @@ #include <arch/io.h> #include <arch/ioapic.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <cpu/x86/smm.h> #include <cbmem.h> #include <string.h> @@ -669,7 +670,7 @@ static void pch_lpc_add_io_resources(struct device *dev) static void pch_lpc_read_resources(struct device *dev) { - global_nvs_t *gnvs; + struct global_nvs *gnvs; /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); @@ -681,9 +682,9 @@ static void pch_lpc_read_resources(struct device *dev) pch_lpc_add_io_resources(dev); /* Allocate ACPI NVS in CBMEM */ - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs)); if (!acpi_is_wakeup_s3() && gnvs) - memset(gnvs, 0, sizeof(global_nvs_t)); + memset(gnvs, 0, sizeof(struct global_nvs)); } static void pch_lpc_enable(struct device *dev) @@ -695,9 +696,9 @@ static void pch_lpc_enable(struct device *dev) pch_enable(dev); } -static void southbridge_inject_dsdt(const struct device *dev) +void southbridge_inject_dsdt(const struct device *dev) { - global_nvs_t *gnvs; + struct global_nvs *gnvs; gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (!gnvs) { diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h index b5b6e9fc02..4abe026354 100644 --- a/src/southbridge/intel/lynxpoint/nvs.h +++ b/src/southbridge/intel/lynxpoint/nvs.h @@ -4,7 +4,7 @@ #include <stdint.h> #include "vendorcode/google/chromeos/gnvs.h" -typedef struct global_nvs_t { +struct __packed global_nvs { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ u8 smif; /* 0x02 - SMI function call ("TRAP") */ @@ -76,10 +76,6 @@ typedef struct global_nvs_t { /* ChromeOS specific (starts at 0x100)*/ chromeos_acpi_t chromeos; -} __packed global_nvs_t; -check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); +}; -/* Used in SMM to find the ACPI GNVS address */ -global_nvs_t *smm_get_gnvs(void); - -void acpi_create_gnvs(global_nvs_t * gnvs); +check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index 3973a8d94a..77da5351ad 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -205,7 +205,7 @@ static void serialio_init(struct device *dev) } if (config->sio_acpi_mode) { - global_nvs_t *gnvs; + struct global_nvs *gnvs; /* Find ACPI NVS to update BARs */ gnvs = acpi_get_gnvs(); diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index be842c5720..0bc1e2a86f 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -24,8 +24,8 @@ static u8 smm_initialized = 0; /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located * by coreboot. */ -static global_nvs_t *gnvs; -global_nvs_t *smm_get_gnvs(void) +static struct global_nvs *gnvs; +struct global_nvs *smm_get_gnvs(void) { return gnvs; } @@ -325,7 +325,7 @@ static void southbridge_smi_apmc(void) state = smi_apmc_find_state_save(reg8); if (state) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((u32)state->rbx); + gnvs = (struct global_nvs *)((u32)state->rbx); smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h index 99b76e7f76..74324a0cbf 100644 --- a/src/vendorcode/google/chromeos/gnvs.h +++ b/src/vendorcode/google/chromeos/gnvs.h @@ -10,10 +10,10 @@ /* * chromeos_acpi_t portion of ACPI GNVS is assumed to live at - * 0x100 - 0x1000. When defining global_nvs_t, use check_member + * 0x100 - 0x1000. When defining global_nvs, use check_member * to ensure that it is properly aligned: * - * check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); + * check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); */ #define GNVS_CHROMEOS_ACPI_OFFSET 0x100 |